Simulation Results

Simulation Results: uart

22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.39 %

code
96.53 %

assert
98.56 %

func
49.08 %

line
99.48 %

branch
97.67 %

cond
97.43 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		90.91%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	0.870s	288.728us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.650s	55.765us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.760s	18.585us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.480s	933.504us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.730s	15.312us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.860s	40.911us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.760s	18.585us	1	1	100.00
	uart_csr_aliasing	0.730s	15.312us	1	1	100.00

20/22 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	12.400s	11549.839us	1	1	100.00
parity				2	2	100.00
	uart_smoke	0.870s	288.728us	1	1	100.00
	uart_tx_rx	12.400s	11549.839us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	21.430s	22817.176us	1	1	100.00
	uart_rx_parity_err	54.550s	72747.231us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	12.400s	11549.839us	1	1	100.00
	uart_intr	21.430s	22817.176us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	98.690s	156514.674us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	139.680s	140134.647us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	78.020s	101156.936us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	21.430s	22817.176us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	21.430s	22817.176us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	21.430s	22817.176us	1	1	100.00
perf				1	1	100.00
	uart_perf	153.250s	14962.611us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.030s	1446.827us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.030s	1446.827us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	1.080s	2443.091us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	4.270s	4777.249us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.110s	1109.716us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	3.060s	2453.705us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	233.780s	49820.056us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	320.150s	228517.976us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.620s	33.104us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.640s	25.529us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	0.960s	108.998us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	0.960s	108.998us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.650s	55.765us	1	1	100.00
	uart_csr_rw	0.760s	18.585us	1	1	100.00
	uart_csr_aliasing	0.730s	15.312us	1	1	100.00
	uart_same_csr_outstanding	0.740s	23.164us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.650s	55.765us	1	1	100.00
	uart_csr_rw	0.760s	18.585us	1	1	100.00
	uart_csr_aliasing	0.730s	15.312us	1	1	100.00
	uart_same_csr_outstanding	0.740s	23.164us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.730s	43.282us	1	1	100.00
	uart_tl_intg_err	1.140s	78.145us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.140s	78.145us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	15.870s	7627.121us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	38635018649861888916040279434714378583601983710757399252149820623202384974614	75	UVM_ERROR @ 2393656334 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2394830240 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2396047624 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2397438920 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				1 test run
	uart_stress_all	38684910850462385756769063798398788174474095527688955847402369739796344587588	183	UVM_ERROR @ 227737162261 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 227737172570 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (38 [0x26] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 227737193188 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 227737203497 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (38 [0x26] vs 254 [0xfe]) reg name: uart_reg_block.rdata