Simulation Results: sram_ctrl/ret

 
25/06/2026 15:30:31 DVSim: v1.49.11 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.21 %
  • code
  • 83.36 %
  • assert
  • 97.26 %
  • func
  • 93.00 %
  • block
  • 93.83 %
  • line
  • 94.99 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 567.540us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 37.105us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.252us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 196.705us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.760us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 251.106us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 39.252us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.760us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 4445.381us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 211.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 364.955us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 196.000s 4239.703us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 4.000s 147.200us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 11.000s 979.224us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 847.684us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 966.425us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 252.190us 1 1 100.00
sram_ctrl_partial_access_b2b 127.000s 15447.897us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 51.250us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 27.906us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 35.537us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1043.542us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 68.240us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 23.000s 3092.054us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.560us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 144.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 144.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 37.105us 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.252us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.760us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 37.105us 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.252us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.760us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 796.185us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 809.358us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 809.358us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1043.542us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1043.542us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.252us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 966.425us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 966.425us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 966.425us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 847.684us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 35.444us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 796.185us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 134.017us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 567.540us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 567.540us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 966.425us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 847.684us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 567.540us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 443.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 40.000s 16567.496us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 91601191148517908918066672261755368785862072156564676473075956255314343414044 86
UVM_INFO @ 51250269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 30974199466907637711949037570991871434957796961486237891016658052445889789694 86
UVM_INFO @ 27905855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 83162180396821792090270290840665002202992454173759431357549792031338547518736 86
UVM_INFO @ 35536721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 75390943996449904660555990887324693511635385080342177186339883771628188826700 94
UVM_INFO @ 251106181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---