Simulation Results

Simulation Results: i2c

06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.52 %

code
80.92 %

assert
97.67 %

func
80.97 %

line
95.95 %

branch
91.63 %

cond
85.12 %

toggle
89.66 %

FSM
42.26 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	16.130s	1557.366us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.160s	2887.957us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.700s	24.117us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.830s	70.308us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.230s	2543.842us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.260s	28.950us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.960s	21.732us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.830s	70.308us	1	1	100.00
	i2c_csr_aliasing	1.260s	28.950us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.780s	60.158us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	63.860s	3555.952us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	2.580s	672.652us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.960s	112.567us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	80.650s	5369.077us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	61.340s	6968.767us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.000s	212.569us	1	1	100.00
	i2c_host_fifo_fmt_empty	9.870s	646.209us	1	1	100.00
	i2c_host_fifo_reset_rx	4.470s	233.490us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	41.120s	2576.525us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	32.980s	4099.564us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.590s	102.247us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.660s	827.930us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	20.460s	12041.461us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.590s	804.293us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.330s	4227.468us	1	1	100.00
	i2c_target_intr_smoke	4.530s	3525.888us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.030s	249.533us	1	1	100.00
	i2c_target_fifo_reset_tx	1.100s	205.629us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	3.780s	10243.991us	1	1	100.00
	i2c_target_stress_rd	17.330s	4227.468us	1	1	100.00
	i2c_target_intr_stress_wr	2.530s	9340.391us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.830s	4365.019us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	12.540s	1528.391us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.530s	4568.648us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.290s	1385.833us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.550s	232.403us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.160s	318.619us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	2.580s	672.652us	1	1	100.00
	i2c_host_perf_precise	3.050s	1001.337us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	32.980s	4099.564us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.260s	75.169us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	1.840s	2802.593us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.230s	541.704us	1	1	100.00
	i2c_target_nack_txstretch	1.150s	248.996us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.910s	375.505us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.430s	7513.725us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.740s	26.396us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.820s	36.424us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.380s	147.109us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.380s	147.109us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	24.117us	1	1	100.00
	i2c_csr_rw	0.830s	70.308us	1	1	100.00
	i2c_csr_aliasing	1.260s	28.950us	1	1	100.00
	i2c_same_csr_outstanding	1.220s	155.565us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	24.117us	1	1	100.00
	i2c_csr_rw	0.830s	70.308us	1	1	100.00
	i2c_csr_aliasing	1.260s	28.950us	1	1	100.00
	i2c_same_csr_outstanding	1.220s	155.565us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.520s	297.247us	1	1	100.00
	i2c_sec_cm	1.210s	47.431us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.520s	297.247us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	2.860s	305.641us	1
target_error_intr				1
	i2c_target_unexp_stop	1.060s	67.553us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	21.460s	13903.907us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	91874986897366968041522898762137422178258196734986305037261867672530712421554	80	UVM_INFO @ 60158233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	79000946841133621595597608363783052570801194433185802767161365814651054714719	91	UVM_INFO @ 3555951751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	90749608189529661384637271311892726459497421420526061006087710300383231628204	86	UVM_INFO @ 305640501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	19652207494093572765387368810922725223944409540552464955927597036501242504904	95	UVM_INFO @ 13903906781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	38370003735349653128484766896276813836283354653334327136433552761279274666343	84	UVM_INFO @ 827930014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	21647199602533156325660851656617304640053095474771019683317566107326209571124	78	UVM_INFO @ 67553347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	88783301930966628650850907922854552119120624916144166857427630166700339905545	78	UVM_INFO @ 248996086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---