Simulation Results

Simulation Results: i2c

08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.10 %

code
78.19 %

assert
97.04 %

func
77.06 %

line
96.38 %

branch
92.19 %

cond
84.93 %

toggle
74.00 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	46.840s	8139.320us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.620s	3697.610us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.760s	19.500us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.710s	31.573us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.260s	333.539us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.400s	145.753us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.980s	21.887us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.710s	31.573us	1	1	100.00
	i2c_csr_aliasing	1.400s	145.753us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.850s	39.262us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	560.570s	33044.889us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	75.210s	2775.603us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.690s	82.156us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	156.870s	4879.940us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	66.520s	4003.015us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.950s	511.393us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.240s	1558.270us	1	1	100.00
	i2c_host_fifo_reset_rx	5.090s	313.784us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	98.610s	2952.211us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	8.950s	2989.382us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.280s	522.703us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.950s	445.162us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	70.280s	33897.474us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.040s	9821.203us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	31.310s	1022.931us	1	1	100.00
	i2c_target_intr_smoke	4.110s	1131.168us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.680s	198.887us	1	1	100.00
	i2c_target_fifo_reset_tx	1.100s	514.335us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	6.360s	10302.665us	1	1	100.00
	i2c_target_stress_rd	31.310s	1022.931us	1	1	100.00
	i2c_target_intr_stress_wr	405.990s	35566.937us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.780s	2916.314us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.230s	639.490us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.200s	1131.819us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.860s	1704.584us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.080s	942.744us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.170s	318.937us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	75.210s	2775.603us	1	1	100.00
	i2c_host_perf_precise	1.160s	99.651us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	8.950s	2989.382us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.250s	59.669us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.010s	603.361us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.630s	960.799us	1	1	100.00
	i2c_target_nack_txstretch	1.100s	147.078us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.110s	377.584us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.440s	2993.496us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.680s	17.967us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.730s	24.995us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.580s	42.935us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.580s	42.935us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	19.500us	1	1	100.00
	i2c_csr_rw	0.710s	31.573us	1	1	100.00
	i2c_csr_aliasing	1.400s	145.753us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	78.682us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	19.500us	1	1	100.00
	i2c_csr_rw	0.710s	31.573us	1	1	100.00
	i2c_csr_aliasing	1.400s	145.753us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	78.682us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.700s	176.672us	1	1	100.00
	i2c_sec_cm	1.020s	81.329us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.700s	176.672us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.730s	272.994us	1
target_error_intr				1
	i2c_target_unexp_stop	1.190s	643.150us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	19.070s	8126.394us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	54646110343112860230282695016573786061073223593544940005093197476046336489795	85	UVM_INFO @ 39261791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	23945591631845235579636065603201498085885603310838338282786951860640122349260	165	UVM_INFO @ 33044889155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	34927975733925262251580107258719330164667442911912921406251913716190232347158	89	UVM_INFO @ 445161606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!				1 test run
	i2c_target_intr_stress_wr	91225271265574538704499275854777326047733832751513853623324166943331121450165	83	UVM_INFO @ 35566937136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	15673391812098706689595317091839986683873380975586912949223815588999018592318	84	UVM_ERROR @ 643149964 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 643149964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	68059985511063737405133034768612849366713899265818567828608170132481356344389	84	UVM_INFO @ 272993963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	46599452035884782834947740991245066337455266373707107972873622379669295008932	113	UVM_INFO @ 8126394219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	73768260011046871540696555460865970615147819328371954648974752034299053449202	83	UVM_INFO @ 147077515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---