| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sysrst_ctrl_smoke | 1.400s | 2132.229us | 1 | 1 | 100.00 | |
| input_output_inverted | 1 | 1 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 1.520s | 2470.669us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 3.210s | 2144.520us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 1.420s | 2565.759us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.110s | 4012.591us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.650s | 2075.284us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 7.670s | 3057.842us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 3.870s | 3337.203us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 2.560s | 2047.707us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.650s | 2075.284us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 3.870s | 3337.203us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect | 159.770s | 95559.974us | 1 | 1 | 100.00 | |
| combo_detect_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 17.770s | 113381.946us | 1 | 1 | 100.00 | |
| auto_block_key_outputs | 1 | 1 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 2.500s | 3400.800us | 1 | 1 | 100.00 | |
| keyboard_input_triggered_interrupt | 1 | 1 | 100.00 | |||
| sysrst_ctrl_edge_detect | 1.500s | 2453.310us | 1 | 1 | 100.00 | |
| pin_output_keyboard_inversion_control | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 1.800s | 2529.013us | 1 | 1 | 100.00 | |
| pin_input_value_accessibility | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 1.540s | 2168.940us | 1 | 1 | 100.00 | |
| ec_power_on_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 3.260s | 3281.259us | 1 | 1 | 100.00 | |
| flash_write_protect_output | 1 | 1 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 5.150s | 2614.588us | 1 | 1 | 100.00 | |
| ultra_low_power_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ultra_low_pwr | 0.930s | 4921.636us | 1 | 1 | 100.00 | |
| sysrst_ctrl_feature_disable | 1 | 1 | 100.00 | |||
| sysrst_ctrl_feature_disable | 7.530s | 37381.316us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all | 92.620s | 235294.715us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_alert_test | 4.540s | 2010.099us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_intr_test | 1.430s | 2032.221us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 2.920s | 2216.680us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 2.920s | 2216.680us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.110s | 4012.591us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.650s | 2075.284us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 3.870s | 3337.203us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 5.070s | 4793.463us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 7.110s | 4012.591us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.650s | 2075.284us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 3.870s | 3337.203us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 5.070s | 4793.463us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| sysrst_ctrl_sec_cm | 9.010s | 22061.294us | 1 | 1 | 100.00 | |
| sysrst_ctrl_tl_intg_err | 7.590s | 22596.122us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 7.590s | 22596.122us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 8.380s | 22367.917us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) | 1 test run | |||
| sysrst_ctrl_stress_all_with_rand_reset | 67659772997587374148186216170716412489525183207813720436399500273622671417176 | 731 |
UVM_INFO @ 22123111843 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 22319741689 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Issuing reset for run 10/10
UVM_INFO @ 22324741689 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
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