Simulation Results: uart

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.46 %
  • code
  • 91.81 %
  • assert
  • 98.27 %
  • func
  • 57.31 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.73 %
  • toggle
  • 74.12 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.110s 626.911us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 122.041us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 15.832us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.210s 1127.012us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.760s 41.878us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.900s 28.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 15.832us 1 1 100.00
uart_csr_aliasing 0.760s 41.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 4.070s 3629.806us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.110s 626.911us 1 1 100.00
uart_tx_rx 4.070s 3629.806us 1 1 100.00
parity_error 2 2 100.00
uart_intr 3.200s 9351.438us 1 1 100.00
uart_rx_parity_err 13.250s 15851.701us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 4.070s 3629.806us 1 1 100.00
uart_intr 3.200s 9351.438us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 35.630s 135097.805us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.880s 123819.651us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 147.140s 174089.270us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 3.200s 9351.438us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 3.200s 9351.438us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 3.200s 9351.438us 1 1 100.00
perf 1 1 100.00
uart_perf 204.430s 9215.680us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.670s 1546.143us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.670s 1546.143us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 31.680s 58530.064us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.690s 47505.937us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.290s 6498.770us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.510s 2434.191us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 206.670s 42974.181us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 82.770s 224118.542us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.580s 13.032us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 39.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.180s 195.504us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.180s 195.504us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 122.041us 1 1 100.00
uart_csr_rw 0.590s 15.832us 1 1 100.00
uart_csr_aliasing 0.760s 41.878us 1 1 100.00
uart_same_csr_outstanding 0.910s 43.864us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 122.041us 1 1 100.00
uart_csr_rw 0.590s 15.832us 1 1 100.00
uart_csr_aliasing 0.760s 41.878us 1 1 100.00
uart_same_csr_outstanding 0.910s 43.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.870s 88.855us 1 1 100.00
uart_tl_intg_err 1.370s 102.836us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.370s 102.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 18.530s 3575.803us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_noise_filter 902182294153525296585879526295166960208177317651146188834177348738192626553 80
UVM_ERROR @ 58477416358 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 58479475198 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 58480122262 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 58481357566 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 10445710783419453391881885518710017497068053259406011067492841449726355593184 140
UVM_ERROR @ 3529719962 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3530553282 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3531386602 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3532219922 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0