Simulation Results

Simulation Results: i2c

09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.61 %

code
78.81 %

assert
97.46 %

func
80.55 %

line
96.48 %

branch
92.48 %

cond
85.68 %

toggle
74.17 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	21.700s	1010.957us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.830s	7287.242us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.750s	19.799us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.690s	45.106us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.490s	2314.992us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.500s	125.445us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.330s	39.440us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.690s	45.106us	1	1	100.00
	i2c_csr_aliasing	1.500s	125.445us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.020s	65.329us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	132.050s	18822.637us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	135.210s	27366.974us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.650s	26.860us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	134.450s	4207.237us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	80.490s	2326.242us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.800s	252.250us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.380s	323.659us	1	1	100.00
	i2c_host_fifo_reset_rx	5.080s	849.388us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	35.740s	4090.655us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	8.320s	1690.136us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.160s	294.385us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.690s	1789.534us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	308.970s	31251.752us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.390s	6268.016us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	16.460s	600.688us	1	1	100.00
	i2c_target_intr_smoke	2.930s	3027.276us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.870s	509.297us	1	1	100.00
	i2c_target_fifo_reset_tx	0.890s	268.511us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	183.040s	49156.552us	1	1	100.00
	i2c_target_stress_rd	16.460s	600.688us	1	1	100.00
	i2c_target_intr_stress_wr	55.280s	13631.076us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.530s	13873.187us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	2.230s	10008.861us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.390s	6324.047us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	8.440s	10210.638us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.590s	503.528us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.650s	42.333us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	135.210s	27366.974us	1	1	100.00
	i2c_host_perf_precise	1.450s	136.130us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	8.320s	1690.136us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.010s	51.660us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.680s	544.431us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.530s	2030.206us	1	1	100.00
	i2c_target_nack_txstretch	0.970s	267.243us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.930s	10548.609us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.470s	5293.147us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.630s	77.685us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.630s	16.240us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.220s	543.997us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.220s	543.997us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	19.799us	1	1	100.00
	i2c_csr_rw	0.690s	45.106us	1	1	100.00
	i2c_csr_aliasing	1.500s	125.445us	1	1	100.00
	i2c_same_csr_outstanding	0.760s	22.571us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	19.799us	1	1	100.00
	i2c_csr_rw	0.690s	45.106us	1	1	100.00
	i2c_csr_aliasing	1.500s	125.445us	1	1	100.00
	i2c_same_csr_outstanding	0.760s	22.571us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.150s	260.707us	1	1	100.00
	i2c_sec_cm	0.810s	44.878us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.150s	260.707us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	1.810s	111.448us	1
target_error_intr				1
	i2c_target_unexp_stop	0.900s	101.886us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.650s	3710.076us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_stress_all	53171942847467917982030863966787249464624074288951944206947394209172475128305	137	UVM_INFO @ 18822637044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	86158487544453617992732050868379991778099160940086966611275210613920966895342	89	UVM_INFO @ 1789534062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	42971300477952898193783612624115339865258252691168804289829430522750235642328	83	UVM_INFO @ 10008861394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	29539649826212312833068736506867089036348669645110681799567649632251924076637	83	UVM_INFO @ 101886360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	32322670925660893983138295386597582589546354453207069597261494999949719694731	84	UVM_INFO @ 10210637580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	87777276674542804341841384061945130739756615843101721535754549638054390989112	97	UVM_INFO @ 111448015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	36728918264194089132963927405383703683948656350202008710625667252377199927595	96	UVM_INFO @ 3710075912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---