Simulation Results: sram_ctrl/ret

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.91 %
  • code
  • 82.25 %
  • assert
  • 97.26 %
  • func
  • 93.20 %
  • block
  • 93.69 %
  • line
  • 94.91 %
  • branch
  • 89.36 %
  • toggle
  • 78.08 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 105.774us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 53.497us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.326us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 65.122us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.146us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 58.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 67.326us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.146us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 773.830us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 214.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 620.526us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 172.000s 12812.394us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 1287.840us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 14.000s 632.166us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 2996.951us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 3929.993us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 52.040us 1 1 100.00
sram_ctrl_partial_access_b2b 181.000s 20910.495us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 180.116us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 77.118us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 34.886us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 189.339us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 34.813us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 40.000s 12190.025us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.641us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 189.122us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 189.122us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 53.497us 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.326us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.146us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.114us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 53.497us 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.326us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.146us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 86.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 216.747us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 303.608us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 303.608us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 189.339us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 189.339us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.326us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 3929.993us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 3929.993us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 3929.993us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 2996.951us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 466.894us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 216.747us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 115.775us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 105.774us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 105.774us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 3929.993us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 2996.951us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 105.774us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 311.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 30.000s 15842.834us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 95960268673416981126259986289776043589691432423842542553026869770429144726347 86
UVM_INFO @ 180116321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 51433664987990100285455140988583133326239000268476729777017870440878107453833 86
UVM_INFO @ 77117974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 36621968746567666252992857491394617735357030196423312618227061309288187754613 86
UVM_INFO @ 34885739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---