Simulation Results

Simulation Results: uart

15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.40 %

code
91.51 %

assert
98.85 %

func
44.84 %

line
99.17 %

branch
97.44 %

cond
94.75 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	8.590s	5800.149us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.660s	49.274us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.660s	30.240us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.380s	84.441us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.900s	35.307us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.900s	264.601us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.660s	30.240us	1	1	100.00
	uart_csr_aliasing	0.900s	35.307us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	203.480s	56827.815us	1	1	100.00
parity				2	2	100.00
	uart_smoke	8.590s	5800.149us	1	1	100.00
	uart_tx_rx	203.480s	56827.815us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	9.860s	19923.830us	1	1	100.00
	uart_rx_parity_err	109.950s	131775.379us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	203.480s	56827.815us	1	1	100.00
	uart_intr	9.860s	19923.830us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	26.100s	31597.763us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	42.290s	237565.584us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	11.690s	12697.207us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	9.860s	19923.830us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	9.860s	19923.830us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	9.860s	19923.830us	1	1	100.00
perf				1	1	100.00
	uart_perf	131.340s	5003.453us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	12.170s	12288.398us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	12.170s	12288.398us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	8.950s	6356.966us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	26.990s	35587.720us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	17.700s	6353.390us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	3.240s	1489.268us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	430.510s	130314.325us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	12.750s	12763.671us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.660s	11.778us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.680s	14.441us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.600s	107.169us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.600s	107.169us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.660s	49.274us	1	1	100.00
	uart_csr_rw	0.660s	30.240us	1	1	100.00
	uart_csr_aliasing	0.900s	35.307us	1	1	100.00
	uart_same_csr_outstanding	0.860s	34.030us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.660s	49.274us	1	1	100.00
	uart_csr_rw	0.660s	30.240us	1	1	100.00
	uart_csr_aliasing	0.900s	35.307us	1	1	100.00
	uart_same_csr_outstanding	0.860s	34.030us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.840s	71.276us	1	1	100.00
	uart_tl_intg_err	0.830s	181.337us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	0.830s	181.337us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	28.660s	7175.222us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				2 test runs
	uart_noise_filter	31958205185881827636432604657676861802381760890630242147875645586578511659265	77	UVM_ERROR @ 5538566212 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 5538566212 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 5538646212 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 5538646212 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	6365800845972621030970191495669507500975193512895845267856257545843147779268	164	UVM_ERROR @ 4808510165 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 4825568129 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 8/10 UVM_INFO @ 4825651461 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]