Simulation Results: sram_ctrl/ret

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.50 %
  • code
  • 82.28 %
  • assert
  • 97.81 %
  • func
  • 94.40 %
  • block
  • 93.69 %
  • line
  • 94.91 %
  • branch
  • 89.20 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 590.112us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 90.267us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.237us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 320.934us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.749us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 44.916us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 27.237us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.749us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 9100.121us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 393.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 479.390us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 80.000s 1801.008us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1463.061us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 2478.333us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1364.805us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 972.645us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 81.438us 1 1 100.00
sram_ctrl_partial_access_b2b 233.000s 19939.103us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 27.611us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 25.970us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 33.925us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 468.052us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.442us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 13.000s 920.886us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.879us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 283.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 283.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 90.267us 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.237us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.749us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 65.125us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 90.267us 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.237us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.749us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 65.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 628.345us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 156.667us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 156.667us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 468.052us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 468.052us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.237us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 972.645us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 972.645us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 972.645us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1364.805us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 2.000s 42.084us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 628.345us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 238.728us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 590.112us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 590.112us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 972.645us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1364.805us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 590.112us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 485.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 1051.595us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 56829608710959702220095656195841507163821428221436235773202878651987185752327 86
UVM_INFO @ 27610755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 53198590676768969137103178212143439349149297561583100049031705654762914873803 86
UVM_INFO @ 25970451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 89257713839241800814554066957654798629755031223299436124908115203272004430833 86
UVM_INFO @ 33924982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
sram_ctrl_mubi_enc_err 18493479553012119451395177124163478616782036773267641874062259182762019562928 86
TL item was: req: (cip_tl_seq_item@15269) { a_addr: 'ha85a9fc4 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h83 a_opcode: 'h4 a_user: 'h2642a d_param: 'h0 d_source: 'h83 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 42084350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 56267780444528756266656754649190069818596029088587179013648068543246595867731 88
UVM_INFO @ 44916000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---