Simulation Results: spi_device/1r1w

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.86 %
  • code
  • 93.68 %
  • assert
  • 95.40 %
  • func
  • 62.50 %
  • line
  • 98.83 %
  • branch
  • 98.07 %
  • cond
  • 95.41 %
  • toggle
  • 86.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
85.19%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 107.500s 102888.608us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.950s 23.105us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.010s 852.160us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 17.440s 3885.086us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.500s 1203.506us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.570s 151.802us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.010s 852.160us 1 1 100.00
spi_device_csr_aliasing 10.500s 1203.506us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.590s 28.151us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.380s 49.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.680s 55.291us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.650s 3.013us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.640s 7.378us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.030s 449.341us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.030s 449.341us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.670s 14550.596us 1 1 100.00
spi_device_tpm_sts_read 0.730s 111.958us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.920s 4495.109us 1 1 100.00
pass_cmd_filtering 1 2 50.00
spi_device_pass_cmd_filtering 1.690s 320.470us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
pass_addr_translation 1 2 50.00
spi_device_pass_addr_payload_swap 4.430s 10641.396us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
pass_payload_translation 1 2 50.00
spi_device_pass_addr_payload_swap 4.430s 10641.396us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_info_slots 0 1 0.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_read_status 1 2 50.00
spi_device_intercept 4.710s 996.930us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_read_jedec 1 2 50.00
spi_device_intercept 4.710s 996.930us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_read_sfdp 1 2 50.00
spi_device_intercept 4.710s 996.930us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_fast_read 1 2 50.00
spi_device_intercept 4.710s 996.930us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
cmd_read_pipeline 1 2 50.00
spi_device_intercept 4.710s 996.930us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.380s 1345.880us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 8.930s 13814.417us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 8.930s 13814.417us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 8.930s 13814.417us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 8.530s 6314.174us 1 1 100.00
spi_device_read_buffer_direct 2.170s 369.504us 1 1 100.00
cmd_dummy_cycle 1 2 50.00
spi_device_mailbox 8.930s 13814.417us 1 1 100.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
quad_spi 0 1 0.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
dual_spi 0 1 0.00
spi_device_flash_all 101.010s 30125.573us 0 1 0.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.700s 1169.206us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.700s 1169.206us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 39.380s 4428.075us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 107.500s 102888.608us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 0 1 0.00
spi_device_flash_and_tpm_min_idle 16.740s 2481.979us 0 1 0.00
stress_all 1 1 100.00
spi_device_stress_all 29.390s 22833.474us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.610s 14.271us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.660s 11.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.610s 180.405us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.610s 180.405us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 23.105us 1 1 100.00
spi_device_csr_rw 1.010s 852.160us 1 1 100.00
spi_device_csr_aliasing 10.500s 1203.506us 1 1 100.00
spi_device_same_csr_outstanding 1.240s 29.504us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 23.105us 1 1 100.00
spi_device_csr_rw 1.010s 852.160us 1 1 100.00
spi_device_csr_aliasing 10.500s 1203.506us 1 1 100.00
spi_device_same_csr_outstanding 1.240s 29.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.800s 69.213us 1 1 100.00
spi_device_tl_intg_err 4.070s 211.929us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.070s 211.929us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * 2 test runs
spi_device_flash_all 6502137326057672770296748045505439651428826463185098811022885123714639048611 84
UVM_INFO @ 4386643839 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/10
UVM_INFO @ 4386643839 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/10
tl_ul_fuzzy_flash_status_q[i] = 0x243d8c
tl_ul_fuzzy_flash_status_q[i] = 0x220158
spi_device_flash_and_tpm_min_idle 106706497368740089330308860097652767424424632019277997565455315624886052901811 94
UVM_INFO @ 1613715453 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/6
UVM_INFO @ 1613715453 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/6
tl_ul_fuzzy_flash_status_q[i] = 0xb30ac6
tl_ul_fuzzy_flash_status_q[i] = 0x64172a
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 16681874330326958809413836043659700618091988155785147498765104293514788482377 81
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2117496 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2117496 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 82960680265050895469102870150179532010153176826816893746612994574699062191994 81
UVM_ERROR @ 4788255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x270 [1001110000] vs 0x0 [0])
UVM_ERROR @ 4859255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47 [1000111] vs 0x0 [0])
UVM_ERROR @ 4948255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x302 [1100000010] vs 0x0 [0])
UVM_ERROR @ 5029255 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2bb [1010111011] vs 0x0 [0])