Simulation Results

Simulation Results: i2c

29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.49 %

code
82.23 %

assert
96.83 %

func
83.40 %

line
96.72 %

branch
93.04 %

cond
87.90 %

toggle
88.84 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	18.100s	6687.845us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.810s	6370.440us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.900s	75.748us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.670s	35.004us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.080s	2320.095us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.760s	202.452us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.010s	129.145us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.670s	35.004us	1	1	100.00
	i2c_csr_aliasing	1.760s	202.452us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	56.089us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	435.700s	58552.486us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	53.280s	29693.366us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.700s	28.363us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	65.650s	17693.860us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	24.540s	6161.737us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.900s	73.518us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.550s	481.934us	1	1	100.00
	i2c_host_fifo_reset_rx	6.060s	187.703us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	49.680s	3563.932us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	26.880s	12179.040us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.180s	436.767us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.890s	884.221us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	145.010s	29733.203us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.170s	2293.760us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.370s	13414.280us	1	1	100.00
	i2c_target_intr_smoke	5.860s	1112.073us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.630s	225.125us	1	1	100.00
	i2c_target_fifo_reset_tx	1.430s	273.415us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	1190.230s	64796.175us	1	1	100.00
	i2c_target_stress_rd	19.370s	13414.280us	1	1	100.00
	i2c_target_intr_stress_wr	20.560s	7601.290us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.840s	3005.951us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.320s	377.253us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.120s	2761.847us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	5.200s	10026.189us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.630s	1388.611us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.080s	76.142us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	53.280s	29693.366us	1	1	100.00
	i2c_host_perf_precise	84.260s	6068.617us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	26.880s	12179.040us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.590s	85.759us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	1.710s	471.837us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.150s	488.988us	1	1	100.00
	i2c_target_nack_txstretch	1.350s	702.287us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.090s	1096.082us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.380s	391.079us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.790s	50.727us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.810s	19.887us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.130s	660.706us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.130s	660.706us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.900s	75.748us	1	1	100.00
	i2c_csr_rw	0.670s	35.004us	1	1	100.00
	i2c_csr_aliasing	1.760s	202.452us	1	1	100.00
	i2c_same_csr_outstanding	1.280s	110.910us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.900s	75.748us	1	1	100.00
	i2c_csr_rw	0.670s	35.004us	1	1	100.00
	i2c_csr_aliasing	1.760s	202.452us	1	1	100.00
	i2c_same_csr_outstanding	1.280s	110.910us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.920s	265.748us	1	1	100.00
	i2c_sec_cm	0.950s	66.503us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.920s	265.748us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	16.140s	2415.174us	1
target_error_intr				1
	i2c_target_unexp_stop	0.820s	56.701us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	4.100s	1063.951us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	98196511996856658383435404776452551438883690892070503318637859072748685661688	106	UVM_INFO @ 2415174429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	8745800919952700712650085826182160680035351713371322418988463159277942888077	97	UVM_INFO @ 1063951298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	16468645176005111047627215214669591785460804866961316406164357925207439930261	80	UVM_INFO @ 56088775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	76777228589216535223449887109050597215600161636909976493202729777655161409014	89	UVM_INFO @ 884221245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	85412215272749884677236838080465500609602084246732352232220512409046536098634	83	UVM_INFO @ 56700948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	86262793179550733908290337484919860989783276368625718851706675625032478678962	84	UVM_INFO @ 10026189483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	14744597779715089936634596314241475814705050208373416647218309342959445671103	83	UVM_INFO @ 702287356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---