Simulation Results: chip

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.78 %
  • code
  • 81.70 %
  • assert
  • 97.62 %
  • func
  • 42.01 %
  • line
  • 94.33 %
  • branch
  • 93.71 %
  • cond
  • 89.34 %
  • toggle
  • 73.96 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
89.89%
V2S
100.00%
V3
57.69%
unmapped
54.55%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 194.700s 3109.989us 1 1 100.00
chip_sw_example_rom 104.690s 3116.154us 1 1 100.00
chip_sw_example_manufacturer 168.050s 3296.487us 1 1 100.00
chip_sw_example_concurrency 188.500s 4319.366us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 390.510s 7242.667us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 473.860s 6277.027us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 427.610s 6021.590us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5702.080s 35543.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 694.040s 9755.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5702.080s 35543.926us 1 1 100.00
chip_csr_rw 473.860s 6277.027us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 8.510s 161.089us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 378.090s 4436.271us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 378.090s 4436.271us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 378.090s 4436.271us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 462.750s 4413.841us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 462.750s 4413.841us 1 1 100.00
chip_sw_uart_tx_rx_idx1 432.620s 4514.453us 1 1 100.00
chip_sw_uart_tx_rx_idx2 426.930s 4788.427us 1 1 100.00
chip_sw_uart_tx_rx_idx3 451.310s 4582.030us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 374.440s 4358.716us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 481.550s 5139.327us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 738.320s 9450.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 295.110s 5886.029us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 295.110s 5886.029us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 260.590s 3380.380us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 200.630s 3042.129us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 216.630s 4476.169us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 553.800s 8091.337us 1 1 100.00
chip_tap_straps_testunlock0 113.100s 2909.108us 1 1 100.00
chip_tap_straps_rma 447.660s 6463.586us 1 1 100.00
chip_tap_straps_prod 147.560s 3997.214us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 635.150s 6557.606us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 635.150s 6557.606us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 745.650s 8874.691us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1052.680s 10529.323us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 398.830s 4203.550us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 619.480s 6098.964us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4206.470s 18969.725us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.190s 3622.096us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 749.710s 7327.014us 1 1 100.00
chip_sw_hmac_enc_jitter_en 244.450s 4323.797us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1106.100s 10768.456us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 217.890s 3366.217us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 400.060s 6095.449us 1 1 100.00
chip_sw_clkmgr_jitter 172.340s 3385.783us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 250.980s 3751.579us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 832.920s 10727.863us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 355.720s 6335.325us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 196.350s 3296.085us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 355.720s 6335.325us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 169.090s 3682.257us 1 1 100.00
chip_sw_aes_smoketest 236.820s 4399.574us 1 1 100.00
chip_sw_aon_timer_smoketest 205.790s 3314.257us 1 1 100.00
chip_sw_clkmgr_smoketest 214.500s 4281.807us 1 1 100.00
chip_sw_csrng_smoketest 158.700s 3611.381us 1 1 100.00
chip_sw_entropy_src_smoketest 1327.590s 9371.829us 1 1 100.00
chip_sw_gpio_smoketest 247.650s 3746.766us 1 1 100.00
chip_sw_hmac_smoketest 274.110s 4260.809us 1 1 100.00
chip_sw_kmac_smoketest 219.880s 3261.229us 1 1 100.00
chip_sw_otbn_smoketest 1323.500s 8736.007us 1 1 100.00
chip_sw_pwrmgr_smoketest 349.590s 7160.977us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 465.370s 8415.451us 1 1 100.00
chip_sw_rv_plic_smoketest 222.570s 3720.525us 1 1 100.00
chip_sw_rv_timer_smoketest 213.390s 3248.248us 1 1 100.00
chip_sw_rstmgr_smoketest 196.080s 4100.587us 1 1 100.00
chip_sw_sram_ctrl_smoketest 218.550s 3904.373us 1 1 100.00
chip_sw_uart_smoketest 228.270s 4375.015us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 200.550s 2986.376us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 432.100s 6217.170us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9948.690s 61650.020us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3307.270s 15332.007us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 215.870s 6338.076us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1163.730s 15191.624us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 1031.280s 15310.161us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 8058.310s 53432.633us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9643.670s 55553.546us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 87.720s 3032.807us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 87.720s 3032.807us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5702.080s 35543.926us 1 1 100.00
chip_same_csr_outstanding 1720.110s 14681.946us 1 1 100.00
chip_csr_hw_reset 390.510s 7242.667us 1 1 100.00
chip_csr_rw 473.860s 6277.027us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5702.080s 35543.926us 1 1 100.00
chip_same_csr_outstanding 1720.110s 14681.946us 1 1 100.00
chip_csr_hw_reset 390.510s 7242.667us 1 1 100.00
chip_csr_rw 473.860s 6277.027us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 6.480s 61.821us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.420s 36.078us 1 1 100.00
xbar_smoke_large_delays 37.380s 5766.557us 1 1 100.00
xbar_smoke_slow_rsp 42.640s 4424.857us 1 1 100.00
xbar_random_zero_delays 4.600s 30.066us 1 1 100.00
xbar_random_large_delays 175.500s 28572.868us 1 1 100.00
xbar_random_slow_rsp 104.040s 10563.956us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 27.030s 591.769us 1 1 100.00
xbar_error_and_unmapped_addr 22.710s 579.328us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 30.460s 1137.181us 1 1 100.00
xbar_error_and_unmapped_addr 22.710s 579.328us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 40.290s 1418.850us 1 1 100.00
xbar_access_same_device_slow_rsp 570.200s 59855.051us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 14.810s 210.492us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 68.600s 2655.865us 1 1 100.00
xbar_stress_all_with_error 401.910s 16036.750us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 257.380s 6003.013us 1 1 100.00
xbar_stress_all_with_reset_error 38.420s 209.354us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3307.270s 15332.007us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3302.650s 39331.792us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3234.350s 15254.621us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2673.800s 12079.416us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3573.740s 16521.490us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3773.920s 23026.346us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3582.450s 16045.416us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3359.670s 15985.789us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2723.480s 11626.042us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3515.280s 15443.307us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3560.480s 16081.566us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3504.830s 15403.399us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3513.670s 21021.177us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4703.930s 18898.544us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5893.270s 24050.909us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6230.210s 24606.354us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6179.770s 25956.521us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5835.130s 24273.278us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4890.540s 19727.767us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5951.490s 25005.323us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6225.490s 25600.827us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5949.320s 24401.403us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 6009.600s 24130.571us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2578.190s 11444.379us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3296.640s 14917.457us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3316.470s 14801.955us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3468.820s 15520.335us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3044.930s 15395.911us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2574.890s 11967.009us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3351.380s 15025.455us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3388.110s 15467.585us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3261.790s 15505.534us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3102.610s 14489.446us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2665.380s 11676.234us 1 1 100.00
rom_e2e_asm_init_dev 3339.880s 15909.245us 1 1 100.00
rom_e2e_asm_init_prod 3667.610s 18696.003us 1 1 100.00
rom_e2e_asm_init_prod_end 3468.740s 16011.994us 1 1 100.00
rom_e2e_asm_init_rma 3242.760s 15531.395us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6752.750s 29397.926us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6837.530s 30936.118us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6633.690s 30277.374us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3853.060s 18164.111us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3501.450s 35749.174us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3501.450s 35749.174us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 178.610s 3962.156us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.190s 3622.096us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 199.140s 4112.188us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 168.700s 3164.169us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1501.240s 11318.875us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 270.540s 4410.986us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 481.880s 6332.622us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 614.770s 4884.972us 1 1 100.00
chip_plic_all_irqs_10 397.040s 4772.723us 1 1 100.00
chip_plic_all_irqs_20 443.430s 5258.307us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 283.790s 3892.801us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1270.700s 13002.741us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 363.100s 6028.592us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 192.140s 3565.210us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.140s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 948.940s 7731.971us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 914.050s 6806.229us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 1037.230s 9267.708us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10217.450s 257272.589us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 318.780s 4795.648us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 349.590s 7160.977us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 318.780s 4795.648us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 467.370s 9534.711us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 467.370s 9534.711us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 292.680s 7182.932us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 380.790s 5441.872us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 742.960s 6264.961us 1 1 100.00
chip_sw_aes_idle 168.700s 3164.169us 1 1 100.00
chip_sw_hmac_enc_idle 244.720s 4152.230us 1 1 100.00
chip_sw_kmac_idle 143.790s 3018.755us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 381.190s 5201.344us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 314.620s 4819.651us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 382.010s 5225.978us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 476.580s 5465.831us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1033.490s 13099.406us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 477.080s 4661.323us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 405.920s 5108.806us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 506.660s 4938.922us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 388.080s 4850.012us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 478.950s 5247.848us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 432.220s 5574.972us 1 1 100.00
chip_sw_ast_clk_outputs 745.650s 8874.691us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 388.490s 5828.644us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 506.660s 4938.922us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 388.080s 4850.012us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 398.830s 4203.550us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 619.480s 6098.964us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4206.470s 18969.725us 1 1 100.00
chip_sw_aes_enc_jitter_en 228.190s 3622.096us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 749.710s 7327.014us 1 1 100.00
chip_sw_hmac_enc_jitter_en 244.450s 4323.797us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1106.100s 10768.456us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 217.890s 3366.217us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 400.060s 6095.449us 1 1 100.00
chip_sw_clkmgr_jitter 172.340s 3385.783us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 216.950s 3650.812us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 472.570s 5827.183us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 703.410s 7606.694us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4340.720s 25572.054us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 194.030s 3619.073us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 201.420s 4421.184us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 723.620s 7380.485us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 190.770s 3372.235us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 402.840s 5191.638us 1 1 100.00
chip_sw_flash_init_reduced_freq 1257.190s 23583.084us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13418.830s 135128.239us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 745.650s 8874.691us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 435.240s 5783.334us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 319.090s 4469.933us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 948.940s 7731.971us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2568.320s 24693.403us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 162.710s 2492.061us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 617.030s 8960.945us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 197.940s 3986.512us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4079.270s 21704.206us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 248.250s 3931.656us 1 1 100.00
chip_sw_edn_entropy_reqs 928.110s 7461.167us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 248.250s 3931.656us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2568.320s 24693.403us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 198.290s 3618.535us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1740.710s 23822.037us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 589.960s 5536.337us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 619.480s 6098.964us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 436.530s 4057.969us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 398.830s 4203.550us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 4232.090s 43609.602us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1740.710s 23822.037us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 228.670s 4890.917us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 4232.090s 43609.602us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 385.180s 11744.767us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 653.000s 5766.969us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 504.370s 6011.371us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 504.370s 6011.371us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 229.250s 4228.188us 1 1 100.00
chip_sw_hmac_enc_jitter_en 244.450s 4323.797us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 244.720s 4152.230us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1486.630s 9971.993us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 2063.080s 12018.473us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 444.600s 5702.949us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 555.400s 5746.346us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 445.390s 5105.174us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 262.200s 4110.575us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1106.100s 10768.456us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 977.440s 8236.667us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1501.240s 11318.875us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5491.800s 20026.664us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 239.210s 3848.019us 1 1 100.00
chip_sw_kmac_mode_kmac 218.110s 3587.973us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 217.890s 3366.217us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 241.320s 3712.050us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1352.320s 9764.311us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 143.790s 3018.755us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 481.880s 6332.622us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 553.800s 8091.337us 1 1 100.00
chip_tap_straps_rma 447.660s 6463.586us 1 1 100.00
chip_tap_straps_prod 147.560s 3997.214us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 217.060s 3368.551us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1409.920s 11468.942us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 181.090s 3150.464us 0 1 0.00
chip_sw_flash_rma_unlocked 4232.090s 43609.602us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 268.330s 3381.322us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 607.040s 9135.737us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 616.990s 8739.165us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 605.910s 9589.970us 0 1 0.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 455.210s 10457.493us 1 1 100.00
chip_sw_sram_ctrl_execution_main 830.760s 9684.115us 1 1 100.00
chip_prim_tl_access 385.180s 11744.767us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 388.490s 5828.644us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 477.080s 4661.323us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 405.920s 5108.806us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 506.660s 4938.922us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 388.080s 4850.012us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 478.950s 5247.848us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 432.220s 5574.972us 1 1 100.00
chip_tap_straps_dev 553.800s 8091.337us 1 1 100.00
chip_tap_straps_rma 447.660s 6463.586us 1 1 100.00
chip_tap_straps_prod 147.560s 3997.214us 1 1 100.00
chip_rv_dm_lc_disabled 196.280s 7711.524us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 235.930s 4458.249us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 100.810s 3485.085us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 113.180s 4335.842us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 243.840s 4314.089us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2194.390s 42404.123us 1 1 100.00
chip_rv_dm_lc_disabled 196.280s 7711.524us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 799.940s 12940.817us 0 1 0.00
chip_sw_lc_walkthrough_prod 728.550s 13770.715us 0 1 0.00
chip_sw_lc_walkthrough_prodend 863.240s 10404.292us 1 1 100.00
chip_sw_lc_walkthrough_rma 488.960s 7577.671us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2194.390s 42404.123us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 87.670s 3288.692us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 93.290s 3156.005us 1 1 100.00
rom_volatile_raw_unlock 76.040s 2815.135us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4053.780s 17745.568us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4206.470s 18969.725us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 742.960s 6264.961us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 742.960s 6264.961us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 742.960s 6264.961us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 412.550s 4870.696us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1740.710s 23822.037us 1 1 100.00
chip_sw_otbn_mem_scramble 412.550s 4870.696us 1 1 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 525.820s 6399.568us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 263.040s 3839.782us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1740.710s 23822.037us 1 1 100.00
chip_sw_otbn_mem_scramble 412.550s 4870.696us 1 1 100.00
chip_sw_keymgr_key_derivation 1224.990s 8887.399us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 525.820s 6399.568us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 263.040s 3839.782us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 385.070s 4791.759us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 217.060s 3368.551us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 268.330s 3381.322us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 607.040s 9135.737us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 616.990s 8739.165us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 605.910s 9589.970us 0 1 0.00
chip_sw_lc_ctrl_transition 943.910s 16428.317us 1 1 100.00
chip_prim_tl_access 385.180s 11744.767us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 385.180s 11744.767us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 992.330s 7703.109us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 101.000s 3649.227us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1556.420s 27096.466us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 248.480s 7846.837us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 316.520s 7893.069us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 657.170s 9224.209us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1349.390s 25419.651us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 226.760s 6068.878us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 467.370s 9534.711us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1264.000s 16946.183us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 371.070s 4917.401us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 101.000s 3649.227us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 408.060s 7101.805us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 779.340s 11842.943us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 423.100s 6963.102us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 215.210s 4080.209us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 846.080s 13380.947us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 689.890s 8317.856us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1427.420s 16036.720us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2016.070s 37009.780us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 204.920s 4013.371us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 455.210s 10457.493us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 455.210s 10457.493us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1427.420s 16036.720us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 846.080s 13380.947us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 371.070s 4917.401us 1 1 100.00
chip_sw_pwrmgr_smoketest 349.590s 7160.977us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 402.690s 5592.809us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 530.480s 9594.653us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 304.810s 5903.607us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1270.700s 13002.741us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 226.070s 4087.062us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 914.050s 6806.229us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 560.390s 5834.699us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 575.250s 5401.340us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 235.080s 4334.562us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 263.040s 3839.782us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 530.480s 9594.653us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 530.480s 9594.653us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 225.030s 3873.967us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1200.620s 17986.558us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1194.630s 16249.233us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 402.690s 5592.809us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 291.200s 4522.631us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1420.180s 14498.622us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 447.660s 6463.586us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 196.280s 7711.524us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 614.770s 4884.972us 1 1 100.00
chip_plic_all_irqs_10 397.040s 4772.723us 1 1 100.00
chip_plic_all_irqs_20 443.430s 5258.307us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 182.690s 3015.418us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 158.090s 2617.908us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3307.270s 15332.007us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 239.040s 4410.328us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 234.600s 3757.304us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 261.380s 3804.349us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 199.070s 3466.245us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 525.820s 6399.568us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 400.060s 6095.449us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 607.570s 10766.395us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 553.910s 10933.509us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 830.760s 9684.115us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
chip_sw_data_integrity_escalation 635.150s 6557.606us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 689.890s 8317.856us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1195.650s 24669.293us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 202.740s 3609.217us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 283.670s 4777.535us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 324.020s 4372.501us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1195.650s 24669.293us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1195.650s 24669.293us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2452.330s 21103.573us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2452.330s 21103.573us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 331.030s 5741.807us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3501.450s 35749.174us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 221.080s 2963.237us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 223.180s 2955.803us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 355.470s 3885.663us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 393.330s 4386.155us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1109.710s 9260.499us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5736.980s 32930.836us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2120.880s 13467.928us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 198.980s 3188.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 257.100s 3776.986us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 145.220s 3476.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12292.310s 69041.492us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1178.390s 6423.265us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 609.670s 6779.096us 0 1 0.00
rom_e2e_jtag_debug_dev 243.070s 5413.826us 0 1 0.00
rom_e2e_jtag_debug_rma 209.350s 4137.432us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 134.580s 3756.659us 0 1 0.00
rom_e2e_jtag_inject_dev 85.380s 2565.898us 0 1 0.00
rom_e2e_jtag_inject_rma 87.760s 3449.076us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 116.280s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 334.480s 4453.474us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 362.340s 4124.975us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 774.930s 5120.555us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1678.010s 10827.151us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 297.200s 2645.589us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 694.520s 6824.912us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 198.110s 3496.509us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 235.920s 3234.012us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 347.920s 7289.787us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 366.700s 6901.724us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1427.420s 16036.720us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 609.670s 6779.096us 0 1 0.00
rom_e2e_jtag_debug_dev 243.070s 5413.826us 0 1 0.00
rom_e2e_jtag_debug_rma 209.350s 4137.432us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 236.280s 3287.782us 0 1 0.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 564.830s 5821.369us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5682.010s 38976.801us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5682.010s 38976.801us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 219.930s 4074.349us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 462.750s 4413.841us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3362.020s 19681.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 11 54.55
chip_sival_flash_info_access 230.320s 3941.788us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 22.400s 10.240us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.200s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 200.310s 3119.217us 1 1 100.00
chip_sw_otp_ctrl_descrambling 260.970s 4196.178us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 291.910s 4886.656us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.061s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 240.050s 3805.898us 1 1 100.00
ate_bootstrap_flash_erase 673.490s 10010.400us 0 1 0.00
ate_bootstrap_one_frame 6696.520s 43802.059us 1 1 100.00
ate_bootstrap_disjoint 10031.350s 79678.129us 1 1 100.00

Error Messages

   Test seed line log context
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 80963952473528555959177060882085787220077817121890042624920467989516000629107 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 102777553355278409466498407169071249908144723371783313320854809502930956925890 355
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 110121778255508914441263741112994355504184607661757672091844576303868902730218 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 84936200716948653273761050246805421203896128024433160646576293332259694655470 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 85764638877950539327646830657555465283036264693110717940512236269243405135323 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 22367853177429373159149554742585939484604404416096223979467120695306375131269 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 113898696734370527824425249998044469009606768398602534678835390309695204210608 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 54195357883533702506988683897661272110157081131610041439884020267193688693476 347
UVM_ERROR @ 13380.947000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13380.947000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2226865821342214278956269763501114330904099153959318490072958142187323003105 317
UVM_ERROR @ 6068.878500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6068.878500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 17935891964208177710346809450577745576739603767496801009427376525045621900209 328
UVM_ERROR @ 7893.069000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7893.069000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 28892808153123633573184152061231935103840950781234521660888431122370378298982 345
UVM_ERROR @ 11842.943000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11842.943000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 23162074405543596588596318286050699921723017915642323806830633958838355858139 322
UVM_ERROR @ 9534.711000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9534.711000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 46654274241209160765621892220659037973532760548096038811862833843875361259368 372
UVM_INFO @ 12940.817432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 55546360879594903251793647742459750140673939975330219545418040131990843113173 372
UVM_INFO @ 13770.714852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 15983195652894022297372836015851572365308441259845520963052491891675700723741 344
UVM_INFO @ 7577.671068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 36902328612017082391760575436983577713030090944368519873039293358471458152978 319
UVM_ERROR @ 3234.011964 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3234.011964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 57835865209673559442501845501822807381313626063163405263258599021480932307469 315
UVM_ERROR @ 2492.061294 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2492.061294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 35611516948129001803292393482302259904054174316658340674053479756429252503804 357
UVM_INFO @ 12018.473483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 47439691942144635038255747644398743714123090438201149731280572035352369445836 339
UVM_INFO @ 20026.663846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 35865269771473694283624029077463982313251447083059926996497965774122246168891 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 45529265425483698861024153573599768466059174155809357509178699778909590509880 None
Another command (pid=574051) is running. Waiting for it to complete on the server (server_pid=262655)...
Another command (pid=582792) is running. Waiting for it to complete on the server (server_pid=262655)...
Another command (pid=520792) is running. Waiting for it to complete on the server (server_pid=262655)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 84986742424002586248621034599691460889504080569052498995807019846539701649521 304
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 83107575755876254397898548103233210831413087700367278925957126288021593293182 330
UVM_INFO @ 3757.303544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 31058866535207028595117470865461423606060471157983926183711565126844385640750 312
UVM_INFO @ 3150.463510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 44107772466010112815354955788877651594611900748366243904984160517798533815447 345
UVM_INFO @ 9589.969678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 21973810862886663752600570551465227900494909826842211031093602545001242809460 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 102026350400568931844518456337403335012142084934825531744970935477578186491017 306
UVM_ERROR @ 3649.227173 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3649.227173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 99871537928935692600887770410366745980530883776705525375039620711957348997919 316
UVM_ERROR @ 4080.208720 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4080.208720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 82327558741272164271544527103006166246490059048820939088801713473300535242918 335
UVM_INFO @ 35749.173737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 22442734247779968439018870062713889715919104630559509618187693174555546409204 310
UVM_INFO @ 4410.985708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 114484407387820244569409260597550790407370154458402025671570756971385557399071 311
UVM_INFO @ 3565.209800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 51222313795556282053909853818571027626484420725596756559114534000544122024180 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 79792012970629203142011286690600767406366809455961638373020919939635514424174 220
TL item was: req: (cip_tl_seq_item@34625) { a_addr: 'h104d8 a_data: 'ha09a856e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1bdbd d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3032.807130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 114085543353638098946980614108929808948043015666904173396857128211586399860364 346
UVM_INFO @ 4453.474363 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 30683711450203703610066209837851826837136794014726535636986668138219122079174 314
UVM_INFO @ 4886.656245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 106730928383925073149159915773526425364246440774907772153939035087338886011822 319
UVM_INFO @ 7289.786669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 60527460147231900419928832681375345614992487481452431193869362779492400094396 332
UVM_INFO @ 14498.622330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 94354191687258448330607071147423128805417935541416897124720065179276224243044 314
UVM_ERROR @ 3287.782120 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3287.782120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 16061242977384087278435584241890831009174482662151578778394827622971074335213 240
UVM_INFO @ 7711.524275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 70942499915711979353713587959395123544374473364870063349882562673067886985934 321
UVM_INFO @ 15191.624256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 20792296592071252840694696019804338660498480293277205029359145951150162707723 332
UVM_INFO @ 15310.161130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 88068293187086814776944253952656995696486111790373463415661231922583140087467 330
UVM_INFO @ 10529.323334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 112741309032675089776303213369662506608696127710368543523488623244386741745597 275
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 70934854394062809042462882716772223197558628489814380697874152611914449325569 330
UVM_ERROR @ 6217.170094 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6217.170094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---