Simulation Results: i2c

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.73 %
  • code
  • 78.86 %
  • assert
  • 96.19 %
  • func
  • 82.14 %
  • line
  • 96.75 %
  • branch
  • 92.69 %
  • cond
  • 85.57 %
  • toggle
  • 74.04 %
  • FSM
  • 45.24 %
Validation stages
V1
100.00%
V2
90.24%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 15.770s 28807.729us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 10.060s 4101.652us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.960s 42.181us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.970s 88.196us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.270s 558.268us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.050s 22.205us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.170s 129.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.970s 88.196us 1 1 100.00
i2c_csr_aliasing 1.050s 22.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.970s 120.325us 1 1 100.00
host_stress_all 1 1 100.00
i2c_host_stress_all 358.000s 24864.744us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 13.810s 13502.048us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 17.072us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 60.180s 13384.231us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 65.920s 2734.527us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.190s 126.191us 1 1 100.00
i2c_host_fifo_fmt_empty 8.830s 997.480us 1 1 100.00
i2c_host_fifo_reset_rx 11.360s 980.859us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 59.150s 4028.427us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 10.390s 1224.411us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 2.460s 255.940us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.150s 9167.821us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 49.500s 39452.197us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.560s 1075.123us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 7.320s 697.936us 1 1 100.00
i2c_target_intr_smoke 6.140s 1686.324us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 2.010s 202.505us 1 1 100.00
i2c_target_fifo_reset_tx 1.860s 458.681us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 144.990s 55177.029us 1 1 100.00
i2c_target_stress_rd 7.320s 697.936us 1 1 100.00
i2c_target_intr_stress_wr 202.440s 18885.376us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.960s 1688.737us 1 1 100.00
target_clock_stretch 0 1 0.00
i2c_target_stretch 6.830s 10027.328us 0 1 0.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.710s 962.386us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.070s 660.721us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.220s 177.311us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.870s 341.341us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 13.810s 13502.048us 1 1 100.00
i2c_host_perf_precise 5.180s 733.486us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 10.390s 1224.411us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 0.970s 3.382us 0 1 0.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 3.200s 5149.984us 1 1 100.00
i2c_target_nack_acqfull_addr 2.180s 450.995us 1 1 100.00
i2c_target_nack_txstretch 1.610s 127.168us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 7.110s 770.775us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.980s 855.924us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.970s 50.639us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.960s 16.832us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.400s 116.721us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.400s 116.721us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.960s 42.181us 1 1 100.00
i2c_csr_rw 0.970s 88.196us 1 1 100.00
i2c_csr_aliasing 1.050s 22.205us 1 1 100.00
i2c_same_csr_outstanding 1.100s 201.137us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.960s 42.181us 1 1 100.00
i2c_csr_rw 0.970s 88.196us 1 1 100.00
i2c_csr_aliasing 1.050s 22.205us 1 1 100.00
i2c_same_csr_outstanding 1.100s 201.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.580s 101.546us 1 1 100.00
i2c_sec_cm 1.160s 49.144us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.580s 101.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 22.340s 743.992us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.040s 503.064us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 9.430s 910.302us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 4922182447810465058684143054682847597010425072959712809077510705833926602498 90
UVM_INFO @ 9167821155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! 1 test run
i2c_target_stretch 111250651676465549217022804051149760121103208846131904216392614595642793201340 84
UVM_INFO @ 10027327502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 25884314219990695314695859816967310202383292721050331958729102770424473744609 84
UVM_INFO @ 503063977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 97944049568680146597801338122249874695804843330881373557145754686620678064650 117
UVM_INFO @ 743991661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_target_stress_all_with_rand_reset 102581469529862654638532742067596999290053053696539839775694322289643646142234 115
UVM_INFO @ 910302140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure 1 test run
i2c_target_tx_stretch_ctrl 106768132990112523840987919720516432265588885754188858973369557044376011027042 127
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 11984416926137106304712257571168206665920309269014681949755813293159647712149 84
UVM_INFO @ 127167670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---