Simulation Results

Simulation Results: sysrst_ctrl

01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
83.21 %

code
93.20 %

assert
95.08 %

func
61.34 %

line
97.36 %

branch
97.48 %

cond
95.51 %

toggle
100.00 %

FSM
75.64 %

Validation stages

V1		100.00%
V2		88.89%
V2S		100.00%
V3		100.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sysrst_ctrl_smoke	4.560s	2110.570us	1	1	100.00
input_output_inverted				1	1	100.00
	sysrst_ctrl_in_out_inverted	5.220s	2451.614us	1	1	100.00
combo_detect_ec_rst				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst	4.760s	2390.988us	1	1	100.00
combo_detect_ec_rst_with_pre_cond				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.810s	2368.661us	1	1	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	2.040s	4063.513us	1	1	100.00
csr_rw				1	1	100.00
	sysrst_ctrl_csr_rw	6.130s	2044.055us	1	1	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	35.860s	41510.651us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	2.010s	2178.187us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.890s	2158.259us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sysrst_ctrl_csr_rw	6.130s	2044.055us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.010s	2178.187us	1	1	100.00

16/18 passed

88.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				1	1	100.00
	sysrst_ctrl_combo_detect	104.250s	113388.002us	1	1	100.00
combo_detect_with_pre_cond				0	1	0.00
	sysrst_ctrl_combo_detect_with_pre_cond	18.000s	41142.624us	0	1	0.00
auto_block_key_outputs				1	1	100.00
	sysrst_ctrl_auto_blk_key_output	6.200s	3023.617us	1	1	100.00
keyboard_input_triggered_interrupt				1	1	100.00
	sysrst_ctrl_edge_detect	7.140s	3655.623us	1	1	100.00
pin_output_keyboard_inversion_control				1	1	100.00
	sysrst_ctrl_pin_override_test	3.720s	2517.569us	1	1	100.00
pin_input_value_accessibility				1	1	100.00
	sysrst_ctrl_pin_access_test	3.760s	2235.353us	1	1	100.00
ec_power_on_reset				1	1	100.00
	sysrst_ctrl_ec_pwr_on_rst	2.170s	2983.125us	1	1	100.00
flash_write_protect_output				1	1	100.00
	sysrst_ctrl_flash_wr_prot_out	8.370s	2608.870us	1	1	100.00
ultra_low_power_test				0	1	0.00
	sysrst_ctrl_ultra_low_pwr	4.270s	4603.847us	0	1	0.00
sysrst_ctrl_feature_disable				1	1	100.00
	sysrst_ctrl_feature_disable	17.540s	40549.059us	1	1	100.00
stress_all				1	1	100.00
	sysrst_ctrl_stress_all	7.170s	15454.513us	1	1	100.00
alert_test				1	1	100.00
	sysrst_ctrl_alert_test	1.740s	2039.424us	1	1	100.00
intr_test				1	1	100.00
	sysrst_ctrl_intr_test	4.760s	2016.318us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sysrst_ctrl_tl_errors	3.280s	2627.029us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sysrst_ctrl_tl_errors	3.280s	2627.029us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	2.040s	4063.513us	1	1	100.00
	sysrst_ctrl_csr_rw	6.130s	2044.055us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.010s	2178.187us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	3.780s	5091.269us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	2.040s	4063.513us	1	1	100.00
	sysrst_ctrl_csr_rw	6.130s	2044.055us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.010s	2178.187us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	3.780s	5091.269us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	sysrst_ctrl_sec_cm	4.600s	22385.569us	1	1	100.00
	sysrst_ctrl_tl_intg_err	21.410s	42914.999us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	sysrst_ctrl_tl_intg_err	21.410s	42914.999us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sysrst_ctrl_stress_all_with_rand_reset	6.970s	6365.131us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	33178847621567552727335925843035888715334656791818180960894248810220277502354	661	UVM_INFO @ 2311347497 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_ERROR @ 4603847497 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 4603847497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	114213450436285228588774769760200221826084814765346808693836844584152237120217	681	UVM_ERROR @ 41142624147 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 41142624147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---