Simulation Results

Simulation Results: sysrst_ctrl

08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
85.15 %

code
91.46 %

assert
91.29 %

func
72.70 %

line
96.35 %

branch
96.63 %

cond
94.46 %

toggle
100.00 %

FSM
69.87 %

Validation stages

V1		100.00%
V2		88.89%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sysrst_ctrl_smoke	0.920s	2124.320us	1	1	100.00
input_output_inverted				1	1	100.00
	sysrst_ctrl_in_out_inverted	3.030s	2473.847us	1	1	100.00
combo_detect_ec_rst				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst	2.670s	2434.810us	1	1	100.00
combo_detect_ec_rst_with_pre_cond				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.700s	2527.180us	1	1	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	3.320s	6020.726us	1	1	100.00
csr_rw				1	1	100.00
	sysrst_ctrl_csr_rw	1.220s	2103.511us	1	1	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	18.520s	76226.295us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	0.970s	2098.557us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.710s	2118.914us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sysrst_ctrl_csr_rw	1.220s	2103.511us	1	1	100.00
	sysrst_ctrl_csr_aliasing	0.970s	2098.557us	1	1	100.00

16/18 passed

88.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				1	1	100.00
	sysrst_ctrl_combo_detect	31.750s	60701.024us	1	1	100.00
combo_detect_with_pre_cond				1	1	100.00
	sysrst_ctrl_combo_detect_with_pre_cond	73.810s	170387.897us	1	1	100.00
auto_block_key_outputs				0	1	0.00
	sysrst_ctrl_auto_blk_key_output	31.726s	0.000us	0	1	0.00
keyboard_input_triggered_interrupt				1	1	100.00
	sysrst_ctrl_edge_detect	1.060s	3803.752us	1	1	100.00
pin_output_keyboard_inversion_control				1	1	100.00
	sysrst_ctrl_pin_override_test	2.960s	2514.905us	1	1	100.00
pin_input_value_accessibility				1	1	100.00
	sysrst_ctrl_pin_access_test	1.330s	2023.835us	1	1	100.00
ec_power_on_reset				1	1	100.00
	sysrst_ctrl_ec_pwr_on_rst	1.300s	3705.296us	1	1	100.00
flash_write_protect_output				1	1	100.00
	sysrst_ctrl_flash_wr_prot_out	3.370s	2612.153us	1	1	100.00
ultra_low_power_test				0	1	0.00
	sysrst_ctrl_ultra_low_pwr	0.880s	3972.090us	0	1	0.00
sysrst_ctrl_feature_disable				1	1	100.00
	sysrst_ctrl_feature_disable	8.590s	29234.493us	1	1	100.00
stress_all				1	1	100.00
	sysrst_ctrl_stress_all	24.270s	93391.564us	1	1	100.00
alert_test				1	1	100.00
	sysrst_ctrl_alert_test	2.550s	2013.157us	1	1	100.00
intr_test				1	1	100.00
	sysrst_ctrl_intr_test	1.300s	2030.840us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sysrst_ctrl_tl_errors	2.310s	2228.518us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sysrst_ctrl_tl_errors	2.310s	2228.518us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	3.320s	6020.726us	1	1	100.00
	sysrst_ctrl_csr_rw	1.220s	2103.511us	1	1	100.00
	sysrst_ctrl_csr_aliasing	0.970s	2098.557us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	3.370s	4943.237us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	3.320s	6020.726us	1	1	100.00
	sysrst_ctrl_csr_rw	1.220s	2103.511us	1	1	100.00
	sysrst_ctrl_csr_aliasing	0.970s	2098.557us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	3.370s	4943.237us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	sysrst_ctrl_sec_cm	6.620s	22089.241us	1	1	100.00
	sysrst_ctrl_tl_intg_err	23.570s	22209.376us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	sysrst_ctrl_tl_intg_err	23.570s	22209.376us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	sysrst_ctrl_stress_all_with_rand_reset	5.290s	17051.371us	0	1	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1 test run
	sysrst_ctrl_auto_blk_key_output	14078284108589487183623766570166963624770792470844334911130988985228175467178	None	Chronologic VCS simulator copyright 1991-2025 Contains Synopsys proprietary information. Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 8 18:50 2026 Feature removed during lmreread, or wrong SERVER line hostid. Check your license file. Please contact VCS Customer Support at 1-800-VERILOG for more information. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				1 test run
	sysrst_ctrl_ultra_low_pwr	88964366404208182661481249467051948926589848336078802727254788947602589040105	661	UVM_ERROR @ 3972090349 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3972090349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [] vs [*])				1 test run
	sysrst_ctrl_stress_all_with_rand_reset	40709225115399074813264520292185933296168937576346094501013262431637834475121	690	UVM_INFO @ 8376268003 ps: (cip_base_vseq.sv:1233) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Stress w/ reset is done for run 4/10 UVM_INFO @ 8380091424 ps: (cip_base_vseq.sv:1164) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/10 UVM_INFO @ 8380091424 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/287