Simulation Results: rram_ctrl

 
14/09/2026 17:05:42 DVSim: v1.53.0 sha: 0de3053 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 59.67 %
  • code
  • 53.89 %
  • assert
  • 79.77 %
  • func
  • 45.34 %
  • block
  • 87.06 %
  • line
  • 88.80 %
  • branch
  • 71.91 %
  • toggle
  • 38.19 %
  • FSM
  • 16.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rram_ctrl_smoke 3.000s 1009.047us 1 1 100.00
csr_hw_reset 1 1 100.00
rram_ctrl_csr_hw_reset 3.000s 1216.912us 1 1 100.00
csr_rw 1 1 100.00
rram_ctrl_csr_rw 2.000s 294.303us 1 1 100.00
csr_bit_bash 1 1 100.00
rram_ctrl_csr_bit_bash 13.000s 3391.465us 1 1 100.00
csr_aliasing 1 1 100.00
rram_ctrl_csr_aliasing 3.000s 267.776us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rram_ctrl_csr_mem_rw_with_rand_reset 2.000s 143.670us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rram_ctrl_csr_rw 2.000s 294.303us 1 1 100.00
rram_ctrl_csr_aliasing 3.000s 267.776us 1 1 100.00
mem_walk 1 1 100.00
rram_ctrl_mem_walk 2.000s 422.922us 1 1 100.00
mem_partial_access 1 1 100.00
rram_ctrl_mem_partial_access 3.000s 233.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
rram_ctrl_intr_test 2.000s 534.130us 1 1 100.00
alert_test 1 1 100.00
rram_ctrl_alert_test 5.000s 162.822us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rram_ctrl_tl_errors 5.000s 155.276us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rram_ctrl_tl_errors 5.000s 155.276us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rram_ctrl_csr_hw_reset 3.000s 1216.912us 1 1 100.00
rram_ctrl_csr_rw 2.000s 294.303us 1 1 100.00
rram_ctrl_csr_aliasing 3.000s 267.776us 1 1 100.00
rram_ctrl_same_csr_outstanding 3.000s 1525.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
rram_ctrl_csr_hw_reset 3.000s 1216.912us 1 1 100.00
rram_ctrl_csr_rw 2.000s 294.303us 1 1 100.00
rram_ctrl_csr_aliasing 3.000s 267.776us 1 1 100.00
rram_ctrl_same_csr_outstanding 3.000s 1525.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 1 0.00
rram_ctrl_tl_intg_err 2.000s 888.619us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 2 0.00
rram_ctrl_stress_all_with_rand_reset 2.000s 1459.745us 0 1 0.00
rram_ctrl_stress_all 4.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_WARNING [BDTYP] Cannot create an object of type 'rram_ctrl_stress_all_vseq' because it is not registered with the factory. 2 test runs
rram_ctrl_stress_all_with_rand_reset 103437809344072187115550560163448783110300459515197903755209203346608306701329 86
UVM_INFO @ 1459744533 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
Instance Overrides:
rram_ctrl_stress_all 60339730423010809380219847718724401581001811383878838844381596692674982696822 85
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
Instance Overrides:
UVM_FATAL (cip_base_vseq__tl_errors.svh:476) [rram_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_fault) is not inside '{"recov_err", "fatal_std_err", "fatal_err", "fatal_macro_err", "recov_macro_err"} 1 test run
rram_ctrl_tl_intg_err 71092321995763178387073991579748518338124754926644645586586548399820409455125 94
UVM_INFO @ 888618521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---