Simulation Results

Simulation Results: keymgr

27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.99 %

code
98.96 %

assert
97.72 %

func
91.28 %

line
99.20 %

branch
99.09 %

cond
98.20 %

toggle
98.33 %

FSM
100.00 %

Validation stages

V1		98.89%
V2		99.05%
V2S		99.61%
V3		54.00%

178/180 passed

98.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	25.390s	0.000us	50	50	100.00
random				50	50	100.00
	keymgr_random	41.720s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	1.340s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	11.480s	0.000us	5	5	100.00
csr_aliasing				4	5	80.00
	keymgr_csr_aliasing	6.720s	0.000us	4	5	80.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	2.210s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				24	25	96.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
	keymgr_csr_aliasing	6.720s	0.000us	4	5	80.00

832/840 passed

99.05 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				50	50	100.00
	keymgr_cfg_regwen	78.490s	0.000us	50	50	100.00
sideload				198	200	99.00
	keymgr_sideload	17.300s	0.000us	50	50	100.00
	keymgr_sideload_kmac	16.300s	0.000us	50	50	100.00
	keymgr_sideload_aes	32.190s	0.000us	48	50	96.00
	keymgr_sideload_otbn	33.210s	0.000us	50	50	100.00
direct_to_disabled_state				50	50	100.00
	keymgr_direct_to_disabled	18.600s	0.000us	50	50	100.00
lc_disable				48	50	96.00
	keymgr_lc_disable	14.610s	0.000us	48	50	96.00
kmac_error_response				50	50	100.00
	keymgr_kmac_rsp_err	6.960s	0.000us	50	50	100.00
invalid_sw_input				50	50	100.00
	keymgr_sw_invalid_input	42.810s	0.000us	50	50	100.00
invalid_hw_input				50	50	100.00
	keymgr_hwsw_invalid_input	37.890s	0.000us	50	50	100.00
sync_async_fault_cross				50	50	100.00
	keymgr_sync_async_fault_cross	9.250s	0.000us	50	50	100.00
stress_all				48	50	96.00
	keymgr_stress_all	331.010s	0.000us	48	50	96.00
intr_test				50	50	100.00
	keymgr_intr_test	1.240s	0.000us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.460s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	4.130s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	4.130s	0.000us	20	20	100.00
tl_d_outstanding_access				49	50	98.00
	keymgr_csr_hw_reset	1.340s	0.000us	5	5	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
	keymgr_csr_aliasing	6.720s	0.000us	4	5	80.00
	keymgr_same_csr_outstanding	3.260s	0.000us	20	20	100.00
tl_d_partial_access				49	50	98.00
	keymgr_csr_hw_reset	1.340s	0.000us	5	5	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
	keymgr_csr_aliasing	6.720s	0.000us	4	5	80.00
	keymgr_same_csr_outstanding	3.260s	0.000us	20	20	100.00

V2S

1026/1030 passed

99.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
	keymgr_tl_intg_err	5.140s	0.000us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	6.180s	0.000us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	6.180s	0.000us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	6.180s	0.000us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	6.180s	0.000us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	14.920s	0.000us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	5.140s	0.000us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	6.180s	0.000us	20	20	100.00
sec_cm_op_config_regwen				50	50	100.00
	keymgr_cfg_regwen	78.490s	0.000us	50	50	100.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_random	41.720s	0.000us	50	50	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_random	41.720s	0.000us	50	50	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_random	41.720s	0.000us	50	50	100.00
	keymgr_csr_rw	1.600s	0.000us	20	20	100.00
sec_cm_lc_ctrl_intersig_mubi				48	50	96.00
	keymgr_lc_disable	14.610s	0.000us	48	50	96.00
sec_cm_constants_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	37.890s	0.000us	50	50	100.00
sec_cm_intersig_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	37.890s	0.000us	50	50	100.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	41.720s	0.000us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	27.230s	0.000us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_ctrl_fsm_consistency				50	50	100.00
	keymgr_custom_cm	23.160s	0.000us	50	50	100.00
sec_cm_ctrl_fsm_global_esc				48	50	96.00
	keymgr_lc_disable	14.610s	0.000us	48	50	96.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	23.160s	0.000us	50	50	100.00
sec_cm_kmac_if_done_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	23.160s	0.000us	50	50	100.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	23.160s	0.000us	50	50	100.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	15.160s	0.000us	5	5	100.00
sec_cm_ctrl_key_integrity				50	50	100.00
	keymgr_custom_cm	23.160s	0.000us	50	50	100.00

27/50 passed

54.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				27	50	54.00
	keymgr_stress_all_with_rand_reset	23.540s	0.000us	27	50	54.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	keymgr_stress_all_with_rand_reset	69387434489705618260013659175261342369103012187778476406211879620758037056966	380	UVM_ERROR @ 146783953 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 146783953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	46207211965034405181480366465835412561581692093140245986667535235587099807864	453	UVM_ERROR @ 336218554 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 336218554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	35634718040818509728250243670253788985529804927556848528444329558440204802422	1156	UVM_ERROR @ 3624880954 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 3624880954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	18349742824444256446004587785218215491691004581697797867241397839650836344097	211	UVM_ERROR @ 518153939 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 518153939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	58269844600614861856307862181659062395949160072967217801106160996366931255554	782	UVM_ERROR @ 488236331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 488236331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	31542079330484994258831802079127258933276647566328073486925741484004023573422	172	UVM_ERROR @ 115804113 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 115804113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	8903270584879023724171275905334812774627990308383932301701634726413325583208	148	UVM_ERROR @ 177653299 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 177653299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	2731250484320810601201318916407364403657876353809091856435919551520355987941	858	UVM_ERROR @ 690180291 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 690180291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	13709087260798704908410675410384783637295926424855294891268512432061362804980	222	UVM_ERROR @ 456504521 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 456504521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	102528431949065400199503742419120715287206308127251969827074680944629785539284	1280	UVM_ERROR @ 536088762 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 536088762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	99297749367094953689002011669366258597618312607919779800439997366143947107816	277	UVM_ERROR @ 501750336 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 501750336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	71908069151114459004762068188720838498625601936589876037172677689386907716427	171	UVM_ERROR @ 498659062 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 498659062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	5665180944238184169619772011049585790784259454473478384934895222197119427207	133	UVM_ERROR @ 421633498 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 421633498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	107733408197510916390077217153086133099239410221632998711803222012178456932926	412	UVM_ERROR @ 225413705 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 225413705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	97607421741413374361650441762989507696685754407468040908646178828821715513790	149	UVM_ERROR @ 107405910 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 107405910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	100594790562251366924370367901494298565959344501534986606504183316243561117107	472	UVM_ERROR @ 456845314 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 456845314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	4924049497310220510773913946680992972983378765271262959121755804156498117035	777	UVM_ERROR @ 345876135 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 345876135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	39793207492749681199625913211354715125332773012785141273082053161219637129443	1644	UVM_ERROR @ 564771412 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 564771412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	41842456241364241473168993905299426937343619896206048235529506748001069589991	336	UVM_ERROR @ 151927010 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 151927010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	64809753488688338165143885251292298842463816890851180013674761343809762943177	729	UVM_ERROR @ 2490802361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 2490802361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	87113288530540472782814019250571476841994969339923409276349806897997963814249	132	UVM_ERROR @ 163097055 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 163097055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	104538169045516179727571838911060650671158266163942006743763724048744989917880	825	UVM_ERROR @ 1118657514 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1118657514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
	keymgr_lc_disable	26536613166784108095678042091056106721288095146909815209738959790682981544043	92	UVM_ERROR @ 56011945 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000 UVM_INFO @ 56011945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_sideload_aes	102835817746506043406826610975918980529101775834691489844828284758419023312226	90	UVM_ERROR @ 1528356 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 1528356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_sideload_aes	33044852185948162271755267057610694919719427098062404353185313039216787691774	96	UVM_ERROR @ 28639449 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 28639449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	10676997524985934435524740901805391369867816148469233337234162917247790271318	513	UVM_ERROR @ 72641363 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 72641363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all	23769229894021363847272939476817710935598185916577913182912419745613827841298	952	UVM_ERROR @ 919473749 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 919473749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[].used() == (* [] vs [*])
	keymgr_lc_disable	92505481293808718186795709191186257305103461144801152949278891835622900001571	323	UVM_ERROR @ 43943795 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2]) UVM_INFO @ 43943795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share1_output_
	keymgr_stress_all	8415752753853443870736546499060717280813974727816575559404090328811408439970	1281	UVM_ERROR @ 396795811 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4 UVM_INFO @ 396795811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: keymgr_reg_block.err_code reset value:
	keymgr_csr_aliasing	46290024744735266208428063190088532216984491340616474745458111692308676541487	81	UVM_ERROR @ 851200256 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 0 [0x0]) Regname: keymgr_reg_block.err_code reset value: 0x0 UVM_INFO @ 851200256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---