Simulation Results: kmac/unmasked

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 92.38 %
  • assert
  • 97.90 %
  • func
  • 96.68 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.21%
V2S
99.60%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 52.300s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.290s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.280s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.650s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.140s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.570s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.280s 0.000us 20 20 100.00
kmac_csr_aliasing 6.140s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.060s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.740s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2577.030s 0.000us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 771.150s 0.000us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 31.290s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 1415.210s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 996.650s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 800.650s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 1204.980s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 1504.400s 0.000us 5 5 100.00
kmac_test_vectors_kmac 2.590s 0.000us 5 5 100.00
kmac_test_vectors_kmac_xof 2.180s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 363.780s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 257.060s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 240.880s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 311.740s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 289.700s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 11.440s 0.000us 50 50 100.00
sideload_invalid 38 50 76.00
kmac_sideload_invalid 140.950s 0.000us 38 50 76.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 26.510s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 26.750s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 43.830s 0.000us 10 10 100.00
lc_escalation 49 50 98.00
kmac_lc_escalation 22.410s 0.000us 49 50 98.00
stress_all 49 50 98.00
kmac_stress_all 2091.480s 0.000us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 1.060s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.220s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.300s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.300s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.290s 0.000us 5 5 100.00
kmac_csr_rw 1.280s 0.000us 20 20 100.00
kmac_csr_aliasing 6.140s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.440s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.290s 0.000us 5 5 100.00
kmac_csr_rw 1.280s 0.000us 20 20 100.00
kmac_csr_aliasing 6.140s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.440s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.570s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.570s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.570s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.570s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.470s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 53.000s 0.000us 5 5 100.00
kmac_tl_intg_err 4.140s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.140s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
kmac_lc_escalation 22.410s 0.000us 49 50 98.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 52.300s 0.000us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 363.780s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.570s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 53.000s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 53.000s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 53.000s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 52.300s 0.000us 50 50 100.00
sec_cm_fsm_global_esc 49 50 98.00
kmac_lc_escalation 22.410s 0.000us 49 50 98.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 53.000s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 153.730s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 52.300s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 129.770s 0.000us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 8265750615667350674873630605618288691373147093763761219896550099762280000483 84
UVM_FATAL @ 10095733900 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x61b9c000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10095733900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 104009503013768488659258113216687353187838471382357003361068951655704641416856 84
UVM_FATAL @ 10061419094 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfdee4000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10061419094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 70072974793108794262346145886590359568253710654332752961250991006199991313077 84
UVM_FATAL @ 10016819067 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb070d000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10016819067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 89893745538307455422930969050037059472531746434670832263771124105890226152873 381
UVM_ERROR @ 17487050184 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 17487050184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 22166330909462276015978119629030786217129057206821073925949500357852691379842 184
UVM_ERROR @ 6657733094 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6657733094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 79758590070755918181495329697022036347531297490997839824366483480502673150012 86
UVM_FATAL @ 10179068313 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x77498000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10179068313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 34541545922792240621378234227853830690207377267066478933251559316795702084549 94
UVM_FATAL @ 10076729174 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x92d45000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10076729174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
kmac_lc_escalation 7310456717533261114155580987052696234602776038755599056447154354063977976605 None
Please use '-no_save' simv switch to avoid re-execution or '-suppress=ASLR_DETECTED_INFO' to suppress this message.
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 27 20:46 2026
[SCL] Error: One possible reason for this error is that FLEXlm version of the application is higher than the license daemon version. If this is the case, please upgrade the license daemon to latest version (SCL-602)
Fatal License Error.
Internal FLEXlm Error.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
kmac_stress_all 108123699692813363681308004471552792974809361417370295174118397797787541632264 None
Please use '-no_save' simv switch to avoid re-execution or '-suppress=ASLR_DETECTED_INFO' to suppress this message.
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 27 20:46 2026
[SCL] Error: One possible reason for this error is that FLEXlm version of the application is higher than the license daemon version. If this is the case, please upgrade the license daemon to latest version (SCL-602)
Fatal License Error.
Internal FLEXlm Error.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 49070476082373636511662593793800151498591338543774058619086260449174687882229 93
UVM_FATAL @ 10049849295 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcd7a2000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10049849295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 11605037360141196439784867325120672571108891536826711193991072918479637665318 98
UVM_FATAL @ 10495051683 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xedc95000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10495051683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 44212007233322347251496177723917693125404321113246713387477860818111581911773 83
UVM_FATAL @ 10030999734 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbf66000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10030999734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 56045801968549244157551271554456771241069958788452022240960956748471015084136 83
UVM_FATAL @ 10126789484 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7fe60000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10126789484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)
kmac_sideload_invalid 15947519616396715462469470112294064847531065382426931872364120940620167982613 97
UVM_FATAL @ 10343001988 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbe356000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10343001988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 69462961814589446745658645778963520715111435926919899892225781153728262546226 86
UVM_FATAL @ 10127643814 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1c1a3000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10127643814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25)
kmac_sideload_invalid 81392008220204602646058741455559700434439855113205033431737224671572146396607 107
UVM_FATAL @ 12612848494 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf7705000, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 12612848494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 7840102414343001280099611954520405320864815779260241207228325126624221650464 212
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---