Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.95 %
  • code
  • 89.46 %
  • assert
  • 95.99 %
  • func
  • 96.40 %
  • line
  • 97.87 %
  • branch
  • 97.06 %
  • cond
  • 82.83 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.430s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.310s 0.000us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.320s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.010s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.600s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.700s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.320s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.600s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.290s 0.000us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.100s 0.000us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.170s 0.000us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.840s 0.000us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 14.510s 0.000us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_prog_failure 5.840s 0.000us 50 50 100.00
lc_ctrl_errors 14.510s 0.000us 50 50 100.00
lc_ctrl_security_escalation 14.370s 0.000us 50 50 100.00
lc_ctrl_jtag_state_failure 76.780s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.020s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 57.980s 0.000us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.750s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.470s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.890s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 15.190s 0.000us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.750s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.530s 0.000us 10 10 100.00
lc_ctrl_jtag_alert_test 2.950s 0.000us 10 10 100.00
lc_ctrl_jtag_smoke 12.260s 0.000us 20 20 100.00
lc_ctrl_jtag_state_post_trans 33.130s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 20.020s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 57.980s 0.000us 20 20 100.00
lc_ctrl_jtag_access 20.430s 0.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 31.160s 0.000us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 22.120s 0.000us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.530s 0.000us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 436.080s 0.000us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.540s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.290s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.290s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.320s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.600s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.300s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.320s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.600s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.300s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.580s 0.000us 20 20 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.580s 0.000us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.100s 0.000us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.730s 0.000us 50 50 100.00
lc_ctrl_sec_cm 23.710s 0.000us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 14.370s 0.000us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.290s 0.000us 50 50 100.00
lc_ctrl_jtag_state_post_trans 33.130s 0.000us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.010s 0.000us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.010s 0.000us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 16.010s 0.000us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.410s 0.000us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.410s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 148.860s 0.000us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 108289961315753523260149950013697908543111209907300098186223436365291160763642 259
UVM_ERROR @ 3371786818 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3371786818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66279473194266008064982903858647405005878683671690792043178902606320820059129 9192
UVM_ERROR @ 1628424486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1628424486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70280890430720751481753433004907498720618183473698148374131198195753490065324 5233
UVM_ERROR @ 5769100029 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5769100029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72902720032754382744372837894783216679316476261656125090275409227362018500945 1329
UVM_ERROR @ 5579360649 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5579360649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43316300568304641918334550350398398418899829181908551674664090777832173086008 166
UVM_ERROR @ 985693743 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 985693743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61025862887164596142332507184539258107143820517562644502587229449021676951659 1059
UVM_ERROR @ 14359231115 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14359231115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18299208740274430804990815044548690168566634181575853654793671842016705732032 6769
UVM_ERROR @ 23257216073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23257216073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91687750994718624899351119349415463416844665277689182604137972603358157578256 158
UVM_ERROR @ 385158596 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 385158596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52754818825839620870680365034270464654870537827310586755718199137572929263197 438
UVM_ERROR @ 1165596218 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1165596218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71527944316726429281436019718838809253361014307069212770151622925039710855753 2208
UVM_ERROR @ 8721224106 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8721224106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74990035475569255972475188690673113010041245201125529335118227115342486895536 7523
UVM_ERROR @ 3657822826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3657822826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34840803998470976285274929650145107724594696927287035761745730583238446411515 6875
UVM_ERROR @ 1956164947 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1956164947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65755168768307241569063977927199173133204567723178257270491320575631332033754 6593
UVM_ERROR @ 994992187 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 994992187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1199946052718607387526072216219497354055090929551131308308216020776980280726 2192
UVM_ERROR @ 2955300755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2955300755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12175603449089377913961885336515543122841887763108598884582406484718097485532 6979
UVM_ERROR @ 17679164999 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17679164999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62190881510953850386632095754056425788847947780418348236293430239606319233912 256
UVM_ERROR @ 987170900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 987170900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70273437792417623212974859400723165754971426104066602612669585705009265726939 3588
UVM_ERROR @ 6545521044 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6545521044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68431965826897042094454196116704415335313830934222598986245217773438156595524 5005
UVM_ERROR @ 11386926887 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11386926887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34494580482654132052474858964993466970920854365344452653227003148553628418227 5916
UVM_ERROR @ 23377057298 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23377057298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79107686242043235096402291081466442141560363681342619317630672970552880772804 167
UVM_ERROR @ 10038357944 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10038357944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30513830030842797419379226862335350396829280359218247190531050430776259225988 2969
UVM_ERROR @ 5992861179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5992861179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9477840811997762478157136523973509770921909537062308136000576113776428483225 3630
UVM_ERROR @ 4328719809 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4328719809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38286255008103081253350088816914058897145588443361148583119582539301122105543 3532
UVM_ERROR @ 2817835238 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2817835238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32561445445680015412265114258202973799124351081565998268343958217846331996747 7849
UVM_ERROR @ 8008369458 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8008369458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 36235244438452189639993899334968693045382570697900681164794410208801833900771 5291
UVM_ERROR @ 8732072682 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 8732072682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41275597474759059631254174160404461381974513946587892280269814965337880407896 15152
UVM_ERROR @ 28662607259 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 28662607259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*
lc_ctrl_stress_all_with_rand_reset 56699391676508780972247035984949222305669522747912457461379883937648078094799 1706
UVM_ERROR @ 935732143 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestLocked6
UVM_INFO @ 935732143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---