Simulation Results: otbn

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.88 %
  • code
  • 96.68 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 99.50 %
  • line
  • 99.66 %
  • branch
  • 93.64 %
  • toggle
  • 93.42 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.13%
V2S
99.32%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 13.000s 0.000us 1 1 100.00
single_binary 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 11.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 13.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 12.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 11.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 114.000s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 60.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 43.000s 0.000us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 58.000s 0.000us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 76.000s 0.000us 9 10 90.00
stress_all 9 10 90.00
otbn_stress_all 98.000s 0.000us 9 10 90.00
lc_escalation 59 60 98.33
otbn_escalate 27.000s 0.000us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 64.000s 0.000us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 10.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 11.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 11.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 11.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 11.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 11.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 11.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 11.000s 0.000us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 14.263s 0.000us 4 5 80.00
otbn_controller_ispr_rdata_err 9.000s 0.000us 5 5 100.00
otbn_mac_bignum_acc_err 17.000s 0.000us 5 5 100.00
otbn_urnd_err 5.000s 0.000us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 0.000us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 16.000s 0.000us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 77.000s 0.000us 20 20 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
passthru_mem_tl_intg_err 17 20 85.00
otbn_passthru_mem_tl_intg_err 88.000s 0.000us 17 20 85.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 11.000s 0.000us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 77.000s 0.000us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 27.000s 0.000us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 11.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 11.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 27.000s 0.000us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 11.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 0.000us 5 5 100.00
otbn_illegal_mem_acc 7.000s 0.000us 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 17.000s 0.000us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 0.000us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 92.000s 0.000us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 92.000s 0.000us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 13.000s 0.000us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 10.000s 0.000us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 20.000s 0.000us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 20.000s 0.000us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 23.000s 0.000us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 76.000s 0.000us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 14.000s 0.000us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 319.000s 0.000us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 255.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 420.000s 0.000us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 11409774078464697699289209033657827082305181507962306276977826830158160067461 116
UVM_FATAL @ 136247389 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 136247389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 98985446284138338348490731966612330995270767754885574379956581272657479568121 86
UVM_FATAL @ 4409686 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 4409686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 78663587804795676268313763665559589445046785031233799491211893669141026856294 269
UVM_FATAL @ 187437727 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 187437727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 56113692042513087103095933873731510840253174061657154072746774599246712584410 86
UVM_FATAL @ 2929205 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 2929205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_alu_bignum_mod_err 5747298055671499537796169251540668849882379880021593493590839782318537773772 None
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 5747298055671499537796169251540668849882379880021593493590839782318537773772 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_alu_bignum_mod_err/latest
2026/03/28 05:02:13 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
otbn_multi 2611816125439049135211282560837061579475179279309596899642122645117675036104 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 973928436515138994574194977862702545669651304327256695847300020813992476577 123
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17728262 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 17728262 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17728262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 58623448853416082687094538482225080530366906653736475643450119850189579788317 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 26887558 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 26887558 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 26887558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 38984992753625286408873353985317194687987851917957343449544921023586016598984 177
UVM_ERROR @ 1668325630 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1668325630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 24198646691856932669923794525230694448880339344709956551740036306894850081372 171
UVM_ERROR @ 355179352 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 355179352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 27289450906197502417429412030879346756904193709456129896991018017374406179601 432
UVM_ERROR @ 1252760392 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1252760392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 68455184895812086432598917019137593274604620061948076932680073536660556532291 172
UVM_FATAL @ 285630928 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 285630928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 49879620958411295988447755844522389745404807814593894819338940885504151600664 718
UVM_FATAL @ 1553650292 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1553650292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---