Simulation Results: sram_ctrl/main

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.21%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 100.820s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.980s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.320s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.050s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.330s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 419.600s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 158.000s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1070.630s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 341.710s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2270.960s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1089.300s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 85.020s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1221.430s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 86.110s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 521.410s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 102.360s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 94.510s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 96.320s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 942.850s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.300s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7069.840s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.080s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.080s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.980s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.080s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.980s 0.000us 5 5 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.080s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.720s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
sram_ctrl_tl_intg_err 3.010s 0.000us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.010s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 942.850s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 942.850s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.040s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1221.430s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1221.430s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1221.430s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 85.020s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 9.400s 0.000us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.720s 0.000us 20 20 100.00
sec_cm_mem_readback 35 50 70.00
sram_ctrl_readback_err 9.370s 0.000us 35 50 70.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 100.820s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 100.820s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1221.430s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 85.020s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 100.820s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 143.500s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 44765243219419515327167550671908662268849502155385587566857650975257486620477 103
UVM_ERROR @ 1345580522 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x55)
UVM_INFO @ 1345580522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 70613381788057363028850644804114626491848112602126052175935332042345199795016 98
UVM_ERROR @ 2995342550 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x1c)
UVM_INFO @ 2995342550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 34002796703259320544592244315162118225656065544731147740852813212158546190629 103
UVM_ERROR @ 7321699216 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7e) != exp (0x41)
UVM_INFO @ 7321699216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 46601148072063016422945327255949554423909611801995325185635515235350899331107 103
UVM_ERROR @ 693333519 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x6)
UVM_INFO @ 693333519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 11349729500179525102763010680173927670204935042883742129118542318856997414327 103
UVM_ERROR @ 2736257698 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x76)
UVM_INFO @ 2736257698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 114807887401460353362841605371869652123786152977259027651319188317286860362181 103
UVM_ERROR @ 671091335 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0x7f)
UVM_INFO @ 671091335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 52501113691916276251888901235752416501103783173104912166878050271426868833462 103
UVM_ERROR @ 1372051993 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xe) != exp (0x45)
UVM_INFO @ 1372051993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 15781214290651026149973579501117047445459249069796983414149077218306603328566 103
UVM_ERROR @ 675197438 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x4f)
UVM_INFO @ 675197438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54965561540524373733863345948350411275573719139061752500548908076469056134977 103
UVM_ERROR @ 2638048501 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x13)
UVM_INFO @ 2638048501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 45834668915517607961076953521264818342898633123260525450980584671422818288570 103
UVM_ERROR @ 694713250 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x7c)
UVM_INFO @ 694713250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 92442721668396991752132417934330534390380099345787940095656327261009645983615 103
UVM_ERROR @ 2434344443 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5e) != exp (0x41)
UVM_INFO @ 2434344443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 51887209159812644435519106802722106208295168865702853437582589102352429293836 103
UVM_ERROR @ 677544422 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x2a)
UVM_INFO @ 677544422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 26834631538853768585557494695062681613845314961175531433965623031977216849731 103
UVM_ERROR @ 688147404 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x7c)
UVM_INFO @ 688147404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 105363214778777643944448899578321566810727271169627243029904298213834831427978 103
UVM_ERROR @ 1344229531 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x7b)
UVM_INFO @ 1344229531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 39436516644561348117629318205382127433813105610928245007894604222803007498212 103
UVM_ERROR @ 688107922 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1f) != exp (0x71)
UVM_INFO @ 688107922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 61427689122483610637725296032305311249427431992682160406998145714056090503137 105
UVM_ERROR @ 1900315 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1900315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 42022992673436347609743690335152769718781410493695229969460834646179855888122 107
UVM_ERROR @ 6179084 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6179084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 68387693684581661490791604052610986567797289221326932964696161548399681066618 105
UVM_ERROR @ 10343009 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 10343009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 107752425601472170428939880131695120954797206815586856608542405080627371019046 105
UVM_ERROR @ 6181189 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6181189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 48459954436258821527800264718616157589900838161132611793035611912399189988302 105
UVM_ERROR @ 3496230 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3496230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 71123217707954609614698988487120484081927678841105202361184878398420478825138 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 665846588 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 665846588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 51473868735895203645184569683166276498171754247070468071732490288345829041368 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 777886083 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 777886083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 71647509773124577012662551097748866954069995426932354704783074341960834890326 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 6580423154 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 6580423154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 79170027450739132137934242553952324236056588091965887255010109625232390605089 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 694002466 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 694002466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 71963354742730639285235752788713138819469703039747441446086539346854195091614 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 690671733 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 690671733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 111462727112325582947684549257049704642900628150331198520575176737356268872245 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1390093002 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1390093002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 105220271654553929023542131443856773729146341508695914805674196245297315200213 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1401303864 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1401303864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 83608683958390904774862912290904745598345130317677530799180694809350835734357 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 4378295628 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 4378295628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---