Simulation Results: sram_ctrl/ret

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.57%
V2
100.00%
V2S
93.08%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 100.430s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.050s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 0.990s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.040s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.080s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.320s 0.000us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 0.990s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 13.710s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 6.260s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1174.310s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 393.100s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 65.220s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1106.610s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 10.290s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1365.330s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 78.620s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 495.860s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 89.820s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 90.790s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 86.950s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1345.810s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.180s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5773.520s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.020s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.830s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.830s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.990s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.990s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 3.630s 0.000us 19 20 95.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 2.240s 0.000us 20 20 100.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 2.240s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1345.810s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1345.810s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 0.990s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1365.330s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1365.330s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1365.330s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 10.290s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 1.510s 0.000us 44 50 88.00
sec_cm_mem_integrity 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 3.630s 0.000us 19 20 95.00
sec_cm_mem_readback 34 50 68.00
sram_ctrl_readback_err 1.470s 0.000us 34 50 68.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 100.430s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 100.430s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1365.330s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 10.290s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 100.430s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.990s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 672.760s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 29574198062076459077967029378355901597853955722122273814495354020524727151840 103
UVM_ERROR @ 48586586 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 48586586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) sequencer [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_passthru_mem_tl_intg_err 14120119741291097727367880092512310749588588139950512500069212263962044272874 121
UVM_ERROR @ 643946296 ps: (cip_tl_seq_item.sv:227) uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq.tl_seq.req] d_user.data_intg act (0x59) != exp (0x7a)
UVM_INFO @ 643946296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 86609436776011142476359714305062898693460903129064589491021464625643718499593 106
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1919760ps failed at 1919760ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 3308648 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3308648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 28813086533569436053164366039012771734868614444043128493078882837736385432678 107
UVM_ERROR @ 15110548 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 15110548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 30531828139282630187475536967117828364519708236360498106454426577351177687810 105
UVM_ERROR @ 7045202 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7045202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 113338228361123751629612878805789453655797149012997012513745233739104131629050 107
UVM_ERROR @ 13834886 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 13834886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 76895856250269184733315087368830178105203575265492144662405347794777423442168 103
UVM_ERROR @ 26013999 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x67) != exp (0x73)
UVM_INFO @ 26013999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 77799401266253977292861606783250695352416774452745884504605886497539339461793 103
UVM_ERROR @ 307726969 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x4)
UVM_INFO @ 307726969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 55660372310574837687889910278775204500242416618621882152477651291747578729547 103
UVM_ERROR @ 37193751 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x22) != exp (0x1f)
UVM_INFO @ 37193751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 25836022817720476738088236890186823909722317304265930640818830601395049470577 103
UVM_ERROR @ 22443253 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x37)
UVM_INFO @ 22443253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 10424742637133522833661167830337153834414551567363292622196048774922040867748 103
UVM_ERROR @ 46394770 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x29) != exp (0x33)
UVM_INFO @ 46394770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 105575147577288952531748139156071909705434270937086905077053043255952380008207 103
UVM_ERROR @ 242219387 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x22)
UVM_INFO @ 242219387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 41172943939568671332040015279218767229498524999197018694960791607453127704693 103
UVM_ERROR @ 95926957 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x29)
UVM_INFO @ 95926957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 15338723783760950857589911875206943623346033106787924443283280545743357547023 103
UVM_ERROR @ 26836604 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x42) != exp (0x63)
UVM_INFO @ 26836604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 11346877239136350956469163461517136765773390724647425353559248663941403941894 103
UVM_ERROR @ 28072453 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x10) != exp (0x28)
UVM_INFO @ 28072453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 7413363999261819911174147562973356000218875508905872250714681825864012574705 103
UVM_ERROR @ 238118546 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x64)
UVM_INFO @ 238118546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 28771627964273951110539166412933296399712000218993354042456168396344771921314 103
UVM_ERROR @ 22463386 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7b) != exp (0x34)
UVM_INFO @ 22463386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 37654858823586931686961779681457015685850133477557437126230360404864500971835 103
UVM_ERROR @ 26221629 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x6)
UVM_INFO @ 26221629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 88629123009214509940785352877940250106743114566716607694352584243494566251976 103
UVM_ERROR @ 47467391 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x1f)
UVM_INFO @ 47467391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 87438292111734458023280047016372335063286119501182036049096880496041627145138 103
UVM_ERROR @ 22765441 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x23) != exp (0x67)
UVM_INFO @ 22765441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 51287957400082781794099913216873791124003406813309149588486924884852373866730 103
UVM_ERROR @ 58786230 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x51)
UVM_INFO @ 58786230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 61520639051486422185337704689470046098523802978978926478757056975019787055054 103
UVM_ERROR @ 67409908 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x59)
UVM_INFO @ 67409908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 5921286213149010471446845746332798866192337937744200855588748901849830362892 104
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 3086435 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 3086435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 14872787375868364326956158884909827808297120274800031625156230619178843527228 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 141039106 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 141039106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 49682522709058400417572276243972528206145001376401306937083855647439404886292 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 97401366 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 97401366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 14427255711230421738206936385779245524001917023124633957038655990356598430927 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 46621765 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 46621765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 81121017402524263807406795292189291609250906389271548393044891531066333009653 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 26447439 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 26447439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 54904785732347944516219062544298250939113538478496267288615474240256966822899 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 70747474 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 70747474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 17059486169645025349149620781332891690315748826728197460591335631929378711539 109
Offending 'reqfifo_rvalid'
UVM_ERROR @ 37238875 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 37238875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---