Simulation Results: xbar_main

 
27/03/2026 17:03:20 DVSim: v1.16.0 sha: 114d1c4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.25 %
  • code
  • 99.06 %
  • assert
  • 98.69 %
  • func
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 96.25 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
99.11%
Testpoint Test Max Runtime Sim Time Pass Total %
xbar_smoke 50 50 100.00
xbar_smoke 19.920s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
xbar_base_random_sequence 50 50 100.00
xbar_random 184.850s 0.000us 50 50 100.00
xbar_random_delay 298 300 99.33
xbar_smoke_zero_delays 7.710s 0.000us 50 50 100.00
xbar_smoke_large_delays 306.070s 0.000us 50 50 100.00
xbar_smoke_slow_rsp 331.070s 0.000us 50 50 100.00
xbar_random_zero_delays 78.730s 0.000us 50 50 100.00
xbar_random_large_delays 1330.840s 0.000us 50 50 100.00
xbar_random_slow_rsp 1911.290s 0.000us 48 50 96.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 124.840s 0.000us 50 50 100.00
xbar_error_and_unmapped_addr 103.160s 0.000us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 154.620s 0.000us 50 50 100.00
xbar_error_and_unmapped_addr 103.160s 0.000us 50 50 100.00
xbar_all_access_same_device 94 100 94.00
xbar_access_same_device 324.970s 0.000us 50 50 100.00
xbar_access_same_device_slow_rsp 3120.070s 0.000us 44 50 88.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 167.450s 0.000us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 1276.450s 0.000us 50 50 100.00
xbar_stress_all_with_error 1088.160s 0.000us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 1147.610s 0.000us 50 50 100.00
xbar_stress_all_with_reset_error 948.100s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
xbar_access_same_device_slow_rsp 27856446998590156919678340389669932656659625683676130184389343934907490934024 129
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_access_same_device_slow_rsp 63331605273742269642485689503385783137573226582183035227379799544313744612350 170
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_access_same_device_slow_rsp 102313340654619445132277959906196894777469117962217223472585684288139904915633 202
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_access_same_device_slow_rsp 108889203023746523826368817064286815246008016362628217914095055685603552871466 143
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_access_same_device_slow_rsp 99791918282442605295680332419869282546324954338493701005834045157253365929776 128
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_random_slow_rsp 94999051477528259235208309753278889919107470575182950164914342052763628342620 155
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_access_same_device_slow_rsp 57439818946558113307152750771412948986717835052336127688528880349800409829929 172
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xbar_random_slow_rsp 109759855851143384085523041991022482007183062955614820423535744678883285819182 172
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---