Simulation Results: edn/edn0

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.72 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
99.51%
V2S
100.00%
V3
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.340s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.270s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.160s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.140s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.440s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.650s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.160s 0.000us 20 20 100.00
edn_csr_aliasing 1.440s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 2.850s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 2.850s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 2.850s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.440s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.730s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 0.000us 100 100 100.00
disable 92 100 92.00
edn_disable 1.260s 0.000us 50 50 100.00
edn_disable_auto_req_mode 16.310s 0.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 6.110s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.260s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.670s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.350s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.350s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.270s 0.000us 5 5 100.00
edn_csr_rw 1.160s 0.000us 20 20 100.00
edn_csr_aliasing 1.440s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.440s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.270s 0.000us 5 5 100.00
edn_csr_rw 1.160s 0.000us 20 20 100.00
edn_csr_aliasing 1.440s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.440s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.830s 0.000us 20 20 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.060s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.730s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.730s 0.000us 200 200 100.00
edn_sec_cm 8.230s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.730s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.830s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 43 50 86.00
edn_stress_all_with_rand_reset 95.340s 0.000us 43 50 86.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 61297052440394425741161517937887072156753185208422079962525014224475875030216 88
UVM_FATAL @ 200971701 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00587902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 200971701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49101427428371902507961098221340607263673733357124825575787886245135203485641 88
UVM_FATAL @ 49044505 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001d3942 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 49044505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 49882458438773503789673544481233216120363460929043275823101533524685381931577 165
UVM_ERROR @ 1080966409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1080966409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46888504437427043979846939698800648398355062393176454319140026257229737230877 159
UVM_ERROR @ 1459314103 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1459314103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 33703916067536202142004372789613250620178023566411600295606746038615662543548 202
UVM_ERROR @ 1667298244 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1667298244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 12428487842481235668293280597575106015582058316755323450193210074291729715037 208
UVM_ERROR @ 1180175153 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1180175153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 36821309624336371398984413283471661149476608601513300203146371834400432595909 216
UVM_ERROR @ 1432244305 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1432244305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 23082026687730443782121163597891593006433722744434043660664758805807285087812 182
UVM_ERROR @ 1627408288 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1627408288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 98782122430024625534385294288918211807935877558850088653089036379994177072102 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 13793743037424855610539750476851831379190571110958047665200909788076593790970 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2856379845031285235283099389376216906222889942469593881889144773607120460883 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 80574214926929872790396948580225882768241493576634595654945846673403446150170 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110925465984227914526504371411801162936174868518944236736859571490046433254059 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 45463609232326949819069961777166693188281644005791486047342590332084842588607 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (edn_scoreboard.sv:318) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts
edn_stress_all_with_rand_reset 85184349355113082876544350069892081115457729755199966903385586935594627647489 247
UVM_ERROR @ 1017390121 ps: (edn_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (7 [0x7] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 1017390121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---