Simulation Results: edn/edn1

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 96.18 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.21%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.310s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.220s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.250s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.410s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.640s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.030s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.250s 0.000us 20 20 100.00
edn_csr_aliasing 1.640s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 5.810s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 5.810s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 5.810s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.510s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.820s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.720s 0.000us 100 100 100.00
disable 87 100 87.00
edn_disable 1.320s 0.000us 50 50 100.00
edn_disable_auto_req_mode 4.990s 0.000us 37 50 74.00
stress_all 50 50 100.00
edn_stress_all 5.580s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.190s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.330s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.430s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.430s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.220s 0.000us 5 5 100.00
edn_csr_rw 1.250s 0.000us 20 20 100.00
edn_csr_aliasing 1.640s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.740s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.220s 0.000us 5 5 100.00
edn_csr_rw 1.250s 0.000us 20 20 100.00
edn_csr_aliasing 1.640s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.740s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 8.910s 0.000us 20 20 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.080s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.820s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.820s 0.000us 200 200 100.00
edn_sec_cm 4.820s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.820s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 8.910s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 107.930s 0.000us 44 50 88.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 110086310930435364231108246304435909833700275443757817082263101505531572687409 88
UVM_FATAL @ 13853434 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x002469c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 13853434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92659167453863895121535457182942125949414551258691992547380482368292667070099 88
UVM_FATAL @ 58268680 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003b6602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 58268680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 102067308406889811409986953108095298802954102180003070504017131364582819521827 88
UVM_FATAL @ 58194499 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x005c69b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 58194499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43588092934596027264369734416021611379276798761695163481284914988034379321709 88
UVM_FATAL @ 70492199 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00465672 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 70492199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 113876996227436299815381279947495212475292724966767691169537917683397228192085 153
UVM_ERROR @ 1731206271 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1731206271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 36071394482117123609593532342689133389659779385297327204690059439484294439685 129
UVM_ERROR @ 339213171 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 339213171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 108066092019691652489624060903526411940970353600858958825695745349802890339932 213
UVM_ERROR @ 1455195710 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1455195710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 97217283394487877798534008596946619521310721698064752098486104649224191727408 137
UVM_ERROR @ 146963228 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 146963228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37755611252836150596829812546618467529194535304214776855556865998484783349045 337
UVM_ERROR @ 3930548898 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3930548898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102034792353334083210288904694047193986609408881002940454418963297809026570344 323
UVM_ERROR @ 4054398583 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4054398583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 57650320412438817307365725097028175823243701676675385380061637365723607061911 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20935350356477803979555246236205786664822126253451398362534150030233918646274 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66942854650803865596041219716464606509042973961536583767099145334207676369555 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 14032687699780990713944763677501913962426272878343167125649972590271557360242 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109115839116184014672407953334152876436615214979902244378451829429217020074623 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9670939247237124450238226610669739274770801607388176070844229534542003635646 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4812586609580596964776322538096035326633631537107790803548942033472070039330 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106538307942133038533814332202206852496754420712909578001550428175375236871061 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110110789606500022657238819140733682269510224799003556825631855411083261224363 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---