Simulation Results: keymgr

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.77 %
  • code
  • 98.47 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.08 %
  • toggle
  • 98.52 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.17%
V2S
99.32%
V3
56.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 37.700s 0.000us 50 50 100.00
random 50 50 100.00
keymgr_random 48.950s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.500s 0.000us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 24.920s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 8.270s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.160s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_csr_aliasing 8.270s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 47 50 94.00
keymgr_cfg_regwen 70.640s 0.000us 47 50 94.00
sideload 200 200 100.00
keymgr_sideload 41.280s 0.000us 50 50 100.00
keymgr_sideload_kmac 34.780s 0.000us 50 50 100.00
keymgr_sideload_aes 30.210s 0.000us 50 50 100.00
keymgr_sideload_otbn 37.910s 0.000us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 13.660s 0.000us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 5.260s 0.000us 48 50 96.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 5.400s 0.000us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 21.260s 0.000us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 32.640s 0.000us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 11.320s 0.000us 50 50 100.00
stress_all 48 50 96.00
keymgr_stress_all 189.380s 0.000us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.190s 0.000us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.150s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 5.230s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 5.230s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.500s 0.000us 5 5 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_csr_aliasing 8.270s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 3.730s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.500s 0.000us 5 5 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_csr_aliasing 8.270s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 3.730s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 8.900s 0.000us 20 20 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.650s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.650s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.650s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.650s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.940s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.900s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.650s 0.000us 20 20 100.00
sec_cm_op_config_regwen 47 50 94.00
keymgr_cfg_regwen 70.640s 0.000us 47 50 94.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_random 48.950s 0.000us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_random 48.950s 0.000us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.520s 0.000us 20 20 100.00
keymgr_random 48.950s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 5.260s 0.000us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 32.640s 0.000us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 32.640s 0.000us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 48.950s 0.000us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 10.800s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 26.330s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 5.260s 0.000us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 26.330s 0.000us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 26.330s 0.000us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 26.330s 0.000us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.550s 0.000us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 26.330s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 50 56.00
keymgr_stress_all_with_rand_reset 21.810s 0.000us 28 50 56.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
keymgr_stress_all_with_rand_reset 3510947426161078747762050454694640357775010569257786830003887340634595111700 236
UVM_ERROR @ 520153885 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 520153885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1133) [scoreboard] Check failed act != adv_data_a_array[i][j] (* [*] vs * [*]) Adv data to state StOwnerIntKey for Sealing
keymgr_stress_all 101298409498267079536306108688059330611965689288643884572375476214545523434186 1463
UVM_ERROR @ 223356460 ps: (keymgr_scoreboard.sv:1133) [uvm_test_top.env.scoreboard] Check failed act != adv_data_a_array[i][j] (22051633354132563155721537512584970944297740855311253343007103997690685209801 [0x30c0c83cb2d2774780f5a1207a406354ee13a541376c6718d5d5c909d3dcbcc9] vs 22051633354132563155721537512584970944297740855311253343007103997690685209801 [0x30c0c83cb2d2774780f5a1207a406354ee13a541376c6718d5d5c909d3dcbcc9]) Adv data to state StOwnerIntKey for Sealing
UVM_INFO @ 223356460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 39889677559869801092375334282771314326583995961170866303659937760051388133977 115
UVM_ERROR @ 297942520 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 297942520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24910216773386493358402494305967108537989633899037140855776694683005487832399 178
UVM_ERROR @ 111203814 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111203814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 15886765804257013799673951434646819964283459518004686687083421163234264804796 163
UVM_ERROR @ 113830459 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113830459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63396601000617891073633367515303117117627694258977516642824874787311191179952 142
UVM_ERROR @ 459559496 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 459559496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 102711074980300236282330896234874984574603827397870619573321407204568104698739 532
UVM_ERROR @ 889269366 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 889269366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40493267750595102099601546953571625504322765571727684019315724484216219398753 370
UVM_ERROR @ 922313633 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 922313633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 4371336646343585473498406553067373477713111541697732333867404026747953062224 259
UVM_ERROR @ 139746423 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 139746423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 44496145226517623911422512448531118458316275306808692380063167432240381635515 459
UVM_ERROR @ 219176390 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 219176390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 32542227336226592473831368955500630201389230792981465218004704201849251422442 1978
UVM_ERROR @ 5193555663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5193555663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 59377251077685318204271727663508183203129053524099793617400832573514654913257 560
UVM_ERROR @ 312706646 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 312706646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99135519035578034979264290262258086979631148507691551769617791395977557399661 177
UVM_ERROR @ 164333036 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 164333036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 104653226175090521181285527500977769522353858324882610451089094523677817036112 209
UVM_ERROR @ 478566663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 478566663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 15889328307333546414466725887560220738009013256903465205918675928158570489834 392
UVM_ERROR @ 203734495 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 203734495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19631455108705238313262052756392360774524793321702865200212177545563612068768 1195
UVM_ERROR @ 1391236367 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1391236367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 96532597248021774838391442189800307275769541119626134680690170232605344847716 508
UVM_ERROR @ 772893434 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 772893434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43428798274728127173222994849960708040766426462545231259112713534126171906906 138
UVM_ERROR @ 114713656 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114713656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63996996771523954514247925602306780254137422626859751761751629819960504861741 533
UVM_ERROR @ 595489204 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 595489204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 88073973668981085727206186134539768562515432747210241062508515798210910659745 395
UVM_ERROR @ 175407976 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 175407976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23328149167424153383210513248705597813306153727528127533703934483638430446049 1149
UVM_ERROR @ 1344977286 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1344977286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63103775159067801278157291804525406633388734738453584229565898193806059851438 1053
UVM_ERROR @ 275376182 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 275376182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
keymgr_stress_all_with_rand_reset 47843893404491089883903805767525112414746763449473332985381758200387563155668 250
UVM_ERROR @ 220874607 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (57264938237226565317967751560125513211119886832142080436353959212675742142986363846461891440567181140707993699235352445409371858535705870371801218784603568553315231885483008921951154949164441587480409731349765728515264364339500262538878068530013358331168895644673595993570358618722454893522797497406243081883897996444239340975235536206281861046640 [0xefa5e173ef4743c0191abd727c62a47f5171fa9c2fbb4dca9b8d334017b53cf2000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f50769802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 24459183406215967955315575033552373465006801300606064361815348050967505134549204251596154112212519721400651317425676031804882248876809096317396977314425661276925964050097902523244545133761586215192643387476201389150662753494686565683202914739529839769252931823799541239009130153412489514682588546441869548105605705045356911792470781722156399403376 [0x665bf502c52516881b1f375bc43c3c9a0000000000000000df066b812abbc3e7000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f50769802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_cfg_regwen 23512273689890822404751126069568375181553580760158564445138140608801813411967 110
UVM_ERROR @ 19600989 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 19600989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 76989430317788328584381671336026335338655516034621554828017717891318812889819 151
UVM_ERROR @ 145475625 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 145475625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 51157647072778317198596157029857402945689374764395510924612582161530636846583 153
UVM_ERROR @ 5879515 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 5879515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 49190778600180330376329354338755063044990180902832375051823854739266997557260 162
UVM_ERROR @ 92796573 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 92796573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_lc_disable 70076381314669044184537847036051761034291200542558582556744066109950997232709 396
UVM_ERROR @ 167121212 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1548753059 [0x5c5018a3] vs 1548753059 [0x5c5018a3]) reg name: keymgr_reg_block.sw_share1_output_6
UVM_INFO @ 167121212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Sealing Kmac
keymgr_lc_disable 98045179015339080099699540049075241923366544525954464116780726636723873960607 449
UVM_ERROR @ 332615692 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (824445537317976385747138208263836671083420244854227412334104309440085390797653896475223000590475312108600588825560195374547966627945430690292537129829506 [0xfbdce4bb4c6935f0b10238623e7c1d136ac6341b1e3d5686e774606ee996e26357764cbfd1b8f8471c945c5f1dabc0c2e7e6f54943500dd4c4f93bd34520482] vs 824445537317976385747138208263836671083420244854227412334104309440085390797653896475223000590475312108600588825560195374547966627945430690292537129829506 [0xfbdce4bb4c6935f0b10238623e7c1d136ac6341b1e3d5686e774606ee996e26357764cbfd1b8f8471c945c5f1dabc0c2e7e6f54943500dd4c4f93bd34520482]) KMAC key at state StOwnerIntKey for Sealing Kmac
UVM_INFO @ 332615692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---