Simulation Results: otbn

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.89 %
  • code
  • 96.62 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.48 %
  • line
  • 99.65 %
  • branch
  • 93.41 %
  • toggle
  • 93.42 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.42%
V2S
99.39%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 0.000us 1 1 100.00
single_binary 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 11.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 120.000s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 38.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 43.000s 0.000us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 0.000us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 189.000s 0.000us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 112.000s 0.000us 9 10 90.00
lc_escalation 60 60 100.00
otbn_escalate 43.000s 0.000us 60 60 100.00
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 11.000s 0.000us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 23.000s 0.000us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 11.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 11.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 8.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 9.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 10.000s 0.000us 5 5 100.00
otbn_csr_rw 8.000s 0.000us 20 20 100.00
otbn_csr_aliasing 9.000s 0.000us 5 5 100.00
otbn_same_csr_outstanding 9.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 16.000s 0.000us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 20.000s 0.000us 5 5 100.00
otbn_controller_ispr_rdata_err 9.000s 0.000us 5 5 100.00
otbn_mac_bignum_acc_err 33.000s 0.000us 5 5 100.00
otbn_urnd_err 8.000s 0.000us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 0.000us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 0.000us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 12.000s 0.000us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 36.000s 0.000us 20 20 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
passthru_mem_tl_intg_err 17 20 85.00
otbn_passthru_mem_tl_intg_err 92.000s 0.000us 17 20 85.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 16.000s 0.000us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 11.000s 0.000us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 36.000s 0.000us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 43.000s 0.000us 60 60 100.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 16.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 9.000s 0.000us 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 16.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 9.000s 0.000us 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 43.000s 0.000us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 0.000us 10 10 100.00
otbn_dmem_err 16.000s 0.000us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 0.000us 4 5 80.00
otbn_illegal_mem_acc 9.000s 0.000us 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 0.000us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 8.000s 0.000us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 33.000s 0.000us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 33.000s 0.000us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 14.000s 0.000us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 0.000us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 18.000s 0.000us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 18.000s 0.000us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 10.000s 0.000us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 189.000s 0.000us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 21.000s 0.000us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 441.000s 0.000us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 333.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 459.000s 0.000us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 105806761424324737962731671140337517767026836007554098589979555499282297579481 101
UVM_FATAL @ 62600624 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 62600624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 108646086024987404565497672631415585058914628763021084176786915106693241873294 247
UVM_FATAL @ 233610836 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 233610836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 113852988706290962176810252563804764862105127143787868975825324159934351196401 96
UVM_FATAL @ 18677297 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 18677297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 68575085251807364891165487105692901534130746002163994106127516984708291332328 86
UVM_FATAL @ 19626791 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 19626791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 73589277758750790251858151610378178574130503377190757384055187477331040924471 246
UVM_ERROR @ 313745838 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 313745838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 6592798173625774570703745254248642481211252120895141590462487160496179781012 210
UVM_ERROR @ 330738402 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 330738402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 43861964812367104326112197535424594365710755890234683169512645817506676361845 370
UVM_ERROR @ 6253820993 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6253820993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 69693736680319273503167568546666064577118965485433143534918101369284164586074 159
UVM_ERROR @ 755162730 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 755162730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 18272274900298623107123028352058925968426212349370902462621591899783565281797 154
UVM_ERROR @ 129212307 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 129212307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45037581181712174443845128724091091746486642595319381406369876248583753684508 700
UVM_ERROR @ 5787414535 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5787414535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 70099458714084234828941764162152988262968042167383909587186626905432311247293 130
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 96871772 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 96871772 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 96871772 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 96871772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 101194704821826927030937811512306896167904115483882148146204149529013421251160 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21750525 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 21750525 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 21750525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 101618565312214132048483835237070278413500989768889650680095886617417150126164 278
UVM_FATAL @ 6991030913 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 6991030913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_stress_all 64717705649238738189782037993577218059961433583666073238678833417857592349209 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1