Simulation Results

Simulation Results: rstmgr_cnsty_chk

03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

70.00%

unmapped

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	10	70.00
	rstmgr_cnsty_chk_test	3.760s	0.000us	7	10	70.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	77626042261780074722648189070892278543333930079312103884704118900191477482828	175	UVM_ERROR @ 1941057526 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1960577526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1980097526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1999617526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2019137526 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	52235995002338670667741349629887667180700415236951994253364081871217954137438	175	UVM_ERROR @ 1877581420 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1896461420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1915341420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1934221420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1953101420 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	51523389022794076232529876743902277288238044888790578304101534521785431767394	175	UVM_ERROR @ 1925193151 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1944553151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1963913151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1983273151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2002633151 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16