Simulation Results

Simulation Results: spi_host

03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.81 %

code
95.03 %

assert
95.64 %

func
90.76 %

block
96.96 %

line
98.76 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.12%
V2S		100.00%
unmapped		80.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	110.000s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	3.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	0.000us	5	5	100.00

1130/1140 passed

99.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	28.000s	0.000us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	30.000s	0.000us	50	50	100.00
	spi_host_error_cmd	28.000s	0.000us	50	50	100.00
	spi_host_event	251.000s	0.000us	50	50	100.00
clock_rate				48	50	96.00
	spi_host_speed	177.000s	0.000us	48	50	96.00
speed				48	50	96.00
	spi_host_speed	177.000s	0.000us	48	50	96.00
chip_select_timing				48	50	96.00
	spi_host_speed	177.000s	0.000us	48	50	96.00
sw_reset				50	50	100.00
	spi_host_sw_reset	77.000s	0.000us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	28.000s	0.000us	50	50	100.00
cpol_cpha				48	50	96.00
	spi_host_speed	177.000s	0.000us	48	50	96.00
full_cycle				48	50	96.00
	spi_host_speed	177.000s	0.000us	48	50	96.00
duplex				50	50	100.00
	spi_host_smoke	110.000s	0.000us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	110.000s	0.000us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	88.000s	0.000us	50	50	100.00
spien				50	50	100.00
	spi_host_spien	284.000s	0.000us	50	50	100.00
stall				50	50	100.00
	spi_host_status_stall	298.000s	0.000us	50	50	100.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	30.000s	0.000us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	30.000s	0.000us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	28.000s	0.000us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	0.000us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	28.000s	0.000us	5	5	100.00
	spi_host_tl_intg_err	2.000s	0.000us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	2.000s	0.000us	20	20	100.00

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	spi_host_upper_range_clkdiv	713.000s	0.000us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	spi_host_upper_range_clkdiv	21235432698661593967365318368983122526211497018069228785925791098323332020504	139	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_upper_range_clkdiv	80380338557787089596410807496371542991634314612339034230785094395101075425698	157	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_speed	114956673101285533270119457418834314434935626166903300783714477781459645220627	129	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_speed	105160738658087684000807846348769038647528902924934517301401976999147311010394	287	UVM_FATAL @ 10036482523 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xe0fef354, Comparison=CompareOpEq, exp_data=0x0, call_count=55 UVM_INFO @ 10036482523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---