Simulation Results: sram_ctrl/main

 
03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.72%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 110.770s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.820s 0.000us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 0.910s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 1.640s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 0.990s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.450s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 0.910s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.990s 0.000us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 346.230s 0.000us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 183.810s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1397.950s 0.000us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 380.790s 0.000us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2497.470s 0.000us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1327.300s 0.000us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 112.840s 0.000us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1611.330s 0.000us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 108.260s 0.000us 50 50 100.00
sram_ctrl_partial_access_b2b 495.490s 0.000us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 103.200s 0.000us 50 50 100.00
sram_ctrl_throughput_w_partial_write 109.080s 0.000us 50 50 100.00
sram_ctrl_throughput_w_readback 105.630s 0.000us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1690.800s 0.000us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.630s 0.000us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 8089.540s 0.000us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.070s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 3.650s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 3.650s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.820s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.910s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.990s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.080s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.820s 0.000us 5 5 100.00
sram_ctrl_csr_rw 0.910s 0.000us 20 20 100.00
sram_ctrl_csr_aliasing 0.990s 0.000us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.080s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.990s 0.000us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 2.450s 0.000us 20 20 100.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 2.450s 0.000us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1690.800s 0.000us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1690.800s 0.000us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 0.910s 0.000us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1611.330s 0.000us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1611.330s 0.000us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1611.330s 0.000us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 112.840s 0.000us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 10.680s 0.000us 44 50 88.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.990s 0.000us 20 20 100.00
sec_cm_mem_readback 37 50 74.00
sram_ctrl_readback_err 8.980s 0.000us 37 50 74.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 110.770s 0.000us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 110.770s 0.000us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1611.330s 0.000us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 112.840s 0.000us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 110.770s 0.000us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.060s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 369.320s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 76599831454110892977227972041543786698749073769436783391105215713960667681143 98
UVM_ERROR @ 13168486609 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x1)
UVM_INFO @ 13168486609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 75947105277867075682106701708995335971688303954962439326126629951256649843999 98
UVM_ERROR @ 2991983122 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x5e)
UVM_INFO @ 2991983122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 9368659767162378673982081729661903222042755829188641550391254526540179185511 98
UVM_ERROR @ 699035723 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x10)
UVM_INFO @ 699035723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 34672172180372039031612184607770268431341715268465004565826261711826403942132 98
UVM_ERROR @ 673947963 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4a) != exp (0x2)
UVM_INFO @ 673947963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 3891624045672446824149111103261960127008857559249109650482559897665719832712 98
UVM_ERROR @ 5482728968 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x46) != exp (0x44)
UVM_INFO @ 5482728968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 33882626306294118931910791157742832057635706384237627711086328288959377543464 98
UVM_ERROR @ 5056060019 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x9)
UVM_INFO @ 5056060019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 82277010462496408757216939118552258363029925496858812709837407087535576045072 98
UVM_ERROR @ 2344757225 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0xf)
UVM_INFO @ 2344757225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 41872136689913904570756302291136551069774697377684298654576541187406874935764 98
UVM_ERROR @ 2738008929 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x36) != exp (0x7b)
UVM_INFO @ 2738008929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 74056482038536099942658290054427975399237085254786502342828128174566041348907 98
UVM_ERROR @ 677408351 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x31) != exp (0xb)
UVM_INFO @ 677408351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54742579970422906408349495514769518209210064877887866608530202241593077961787 98
UVM_ERROR @ 2628372773 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xa) != exp (0x20)
UVM_INFO @ 2628372773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 1797279310634283862940704711220741348546525624665356126457734814644601735612 98
UVM_ERROR @ 687805650 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x50)
UVM_INFO @ 687805650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 33006972193105584717356697702674469936931110293742021275058079369685686662290 99
UVM_ERROR @ 5199150 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5199150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 68238218267863820550127590206398105302399796993001700293380131564151328168275 104
UVM_ERROR @ 36562157 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 36562157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 97192788156380562513626704618379624356886043824789912207662748638384673639369 99
UVM_ERROR @ 5017593 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5017593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 111335012869622380265758567774625180544610270674629645626853157701296819961002 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2438000 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2438000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 50248515278479755048679202334383546067136569266477096907105200151064195172747 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 701144755 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 701144755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 9889860945680119329942347557531167018190032849709425729725393994808944926024 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 680858564 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 680858564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 14692393894974411432045756033435071907071031103544540871493088784043564014751 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 4756149086 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 4756149086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 29710491049842182745080593624358546559946334073074301907084752651864910028405 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 687381052 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 687381052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 3963491112781744124560174460799225622330339897676952168634424176286516539844 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 659277562 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 659277562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 92324620370902021960941515862605735531052214198498928579414264919094345500587 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 677188296 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 677188296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 110558431260950510751431905882085314213869728473549109111590489791840938140406 99
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 5459014 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 5459014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).
sram_ctrl_readback_err 112596275314639242043074393129715305719731161945917840939014830283358538296107 98
UVM_ERROR @ 669691901 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@5129) { a_addr: 'hef35cc2c a_data: 'h4e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hec a_opcode: 'h0 a_user: 'h24d01 d_param: 'h0 d_source: 'hec d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 669691901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 67678384026507577109700418539224696611386707721982394089372585412938922938866 98
UVM_ERROR @ 2273758544 ps: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@5217) { a_addr: 'h77a35b2c a_data: 'h46 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h98 a_opcode: 'h0 a_user: 'h24135 d_param: 'h0 d_source: 'h98 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 2273758544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---