Simulation Results

Simulation Results: sram_ctrl/ret

03/04/2026 17:01:04 DVSim: v1.16.0 sha: 3ba6465 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.68 %

code
96.12 %

assert
95.79 %

func
98.14 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		98.26%
V2		100.00%
V2S		93.33%
V3		98.00%

226/230 passed

98.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	102.300s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.990s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	0.970s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	1.810s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	0.950s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				16	20	80.00
	sram_ctrl_csr_mem_rw_with_rand_reset	10.010s	0.000us	16	20	80.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	0.970s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	0.950s	0.000us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.580s	0.000us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.950s	0.000us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1296.990s	0.000us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	385.530s	0.000us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	94.980s	0.000us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1367.070s	0.000us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	10.520s	0.000us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1407.250s	0.000us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	76.140s	0.000us	50	50	100.00
	sram_ctrl_partial_access_b2b	542.860s	0.000us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	93.160s	0.000us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	94.440s	0.000us	50	50	100.00
	sram_ctrl_throughput_w_readback	113.520s	0.000us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1228.140s	0.000us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.180s	0.000us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4043.700s	0.000us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.090s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	3.640s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	3.640s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.990s	0.000us	5	5	100.00
	sram_ctrl_csr_rw	0.970s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	0.950s	0.000us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.040s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.990s	0.000us	5	5	100.00
	sram_ctrl_csr_rw	0.970s	0.000us	20	20	100.00
	sram_ctrl_csr_aliasing	0.950s	0.000us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.040s	0.000us	20	20	100.00

V2S

728/780 passed

93.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				19	20	95.00
	sram_ctrl_passthru_mem_tl_intg_err	4.240s	0.000us	19	20	95.00
tl_intg_err				20	25	80.00
	sram_ctrl_tl_intg_err	2.650s	0.000us	20	20	100.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	2.650s	0.000us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1228.140s	0.000us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1228.140s	0.000us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	0.970s	0.000us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1407.250s	0.000us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1407.250s	0.000us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1407.250s	0.000us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	10.520s	0.000us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				43	50	86.00
	sram_ctrl_mubi_enc_err	1.590s	0.000us	43	50	86.00
sec_cm_mem_integrity				19	20	95.00
	sram_ctrl_passthru_mem_tl_intg_err	4.240s	0.000us	19	20	95.00
sec_cm_mem_readback				37	50	74.00
	sram_ctrl_readback_err	1.690s	0.000us	37	50	74.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	102.300s	0.000us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	102.300s	0.000us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1407.250s	0.000us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	10.520s	0.000us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	102.300s	0.000us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.930s	0.000us	0	5	0.00

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				49	50	98.00
	sram_ctrl_stress_all_with_rand_reset	709.390s	0.000us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	85610505167780298308929787002059504793774918260947213311256320501308035975918	98	UVM_ERROR @ 24702070 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0 UVM_INFO @ 24702070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done
	sram_ctrl_csr_mem_rw_with_rand_reset	20362692561803577304029177728193851592374778555062211149641466889907851312973	96	UVM_FATAL @ 10003627146 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done UVM_INFO @ 10003627146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	sram_ctrl_passthru_mem_tl_intg_err	98199361300020874963626755684934757322419220390939231172342535108774920767431	111	UVM_ERROR @ 94663714 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 94663714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	64237408177983947303759701031251534094002376245454111780655745297567178758721	104	UVM_ERROR @ 33493885 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 33493885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_csr_mem_rw_with_rand_reset	36847593957220858965374013323711256629046682814480615042505279969211973041272	98	UVM_ERROR @ 99173363 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 99173363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	23099563403338070157048345660542072034406112209130530813269382474797999172045	99	UVM_ERROR @ 5269432 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 5269432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	60995323503896317606852281909395452633937020522513178452411119804958312066203	99	UVM_ERROR @ 3512179 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3512179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
	sram_ctrl_sec_cm	50509509602545209981513865332553186911971444240732331533348518098220261175562	99	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 1034659 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 1034659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	91587813576710423592529987275342510554494998674428109756745102151116454320336	101	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 8289679 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 8289679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	29590464858515224215736558072912604362140211986036621438833758923731507596465	98	UVM_ERROR @ 22865145 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1b) != exp (0x2d) UVM_INFO @ 22865145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	17462832868952482407279400406025054586573739503708965018717703504209969227167	98	UVM_ERROR @ 128466039 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x5f) UVM_INFO @ 128466039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	32963349787411433698313024791647889007640683403737184396935398360751820137620	98	UVM_ERROR @ 23756855 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x42) UVM_INFO @ 23756855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	64213274873726565285745658521406659051501842953034677776663253714028901807990	98	UVM_ERROR @ 23458211 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x10) UVM_INFO @ 23458211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	19177493033342851752925649504232233656012995029005517090681202984140432613973	98	UVM_ERROR @ 89714189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x5e) UVM_INFO @ 89714189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	11988226050146241612365242028212072188790907295826551694468559339066158599855	98	UVM_ERROR @ 85020867 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x25) UVM_INFO @ 85020867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	46810999353716941415270573080887778443563654692522981972029160700973817082906	98	UVM_ERROR @ 45026531 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x7a) UVM_INFO @ 45026531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	55928151025839509296791128022228073204864219029644968337585255335224913752705	98	UVM_ERROR @ 52585209 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x17) != exp (0x47) UVM_INFO @ 52585209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	78329515002104876803444490787243682586088997449386866605506967706519307412750	98	UVM_ERROR @ 27578632 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x18) != exp (0x72) UVM_INFO @ 27578632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	69914811762278019464516024574229675627697546285681602199416585267762256893363	98	UVM_ERROR @ 24850192 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x47) != exp (0x72) UVM_INFO @ 24850192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	65753486984042953740095317107230193772802153378728467851984935090660463757228	98	UVM_ERROR @ 49944003 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0x52) UVM_INFO @ 49944003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	98619818989725578879110650016179804559078373720567248519729214735277399801272	98	UVM_ERROR @ 52291988 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x7e) UVM_INFO @ 52291988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	41954454236699003042935908714022210694976545729534247792453395297885370818307	98	UVM_ERROR @ 88000200 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x36) UVM_INFO @ 88000200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	sram_ctrl_sec_cm	14727970732117517066296033077350778977837507672053249479976790553235503790268	100	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1628414ps failed at 1628414ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1638618ps failed at 1638618ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	53541579529278930962722970421611782769061279855133188303461182616274718518810	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 90858555 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 90858555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	96875563127410417760335167274033653121782011751453887954625907079567002510612	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 107266048 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 107266048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	6713146472636721404373589127511914466925127890098892282405163987387444810283	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 181061135 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 181061135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	55737287849395432864219479997504571887889034013435580611805512074047541990590	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 92956513 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 92956513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	43600923721749462557822559267437643522203817635832070796015735993900203588871	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 29838173 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 29838173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	65305783104524637814165502477751128967982371196451926852539187814689926446198	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 41100889 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 41100889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	53735700957744474423860727873188853526402079127466857322962155398516166190655	104	Offending 'reqfifo_rvalid' UVM_ERROR @ 433084431 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 433084431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	sram_ctrl_stress_all_with_rand_reset	5190455788017099999779559588606853105353298378745755435260723353443497476668	180	UVM_ERROR @ 1914056181 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1914056181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---