Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.85 %
  • code
  • 89.35 %
  • assert
  • 95.99 %
  • func
  • 96.22 %
  • line
  • 97.87 %
  • branch
  • 96.85 %
  • cond
  • 82.51 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 9.660s 1007.017us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.190s 87.780us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.290s 46.600us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.290s 248.326us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.350s 105.913us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.830s 121.943us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.290s 46.600us 20 20 100.00
lc_ctrl_csr_aliasing 1.350s 105.913us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.080s 732.309us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.280s 325.592us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.040s 15.565us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.320s 566.747us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 12.410s 1453.084us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_prog_failure 3.320s 566.747us 50 50 100.00
lc_ctrl_errors 12.410s 1453.084us 50 50 100.00
lc_ctrl_security_escalation 9.710s 395.799us 50 50 100.00
lc_ctrl_jtag_state_failure 53.680s 10140.977us 20 20 100.00
lc_ctrl_jtag_prog_failure 22.360s 1189.452us 20 20 100.00
lc_ctrl_jtag_errors 88.640s 7407.106us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 13.170s 770.728us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.250s 569.065us 20 20 100.00
lc_ctrl_jtag_prog_failure 22.360s 1189.452us 20 20 100.00
lc_ctrl_jtag_errors 88.640s 7407.106us 20 20 100.00
lc_ctrl_jtag_access 24.690s 3100.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 28.550s 7169.465us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.880s 789.802us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.040s 2477.742us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 18.810s 2411.858us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.700s 781.749us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.500s 104.139us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.210s 473.712us 10 10 100.00
lc_ctrl_jtag_alert_test 1.660s 186.538us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 26.510s 7172.208us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.500s 19.915us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 654.270s 28744.720us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.710s 51.783us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.450s 152.142us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.450s 152.142us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.190s 87.780us 5 5 100.00
lc_ctrl_csr_rw 1.290s 46.600us 20 20 100.00
lc_ctrl_csr_aliasing 1.350s 105.913us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.110s 45.532us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.190s 87.780us 5 5 100.00
lc_ctrl_csr_rw 1.290s 46.600us 20 20 100.00
lc_ctrl_csr_aliasing 1.350s 105.913us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.110s 45.532us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
lc_ctrl_tl_intg_err 4.420s 456.148us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.420s 456.148us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.280s 325.592us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 12.420s 2775.126us 50 50 100.00
lc_ctrl_sec_cm 8.410s 780.668us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 9.710s 395.799us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.080s 732.309us 50 50 100.00
lc_ctrl_jtag_state_post_trans 15.250s 569.065us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.530s 561.019us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.530s 561.019us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 14.110s 719.829us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.990s 2979.061us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.990s 2979.061us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
lc_ctrl_stress_all_with_rand_reset 172.040s 20870.101us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 4195182129383403240199770023388009610179250610737724535382297349766344014937 4721
UVM_INFO @ 15371962263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23424383803406023075030415553705157376127830886110890014297899676277090044390 1155
UVM_INFO @ 2180834257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 77298314406038059530701185796123328756169564142282702628701671863295799036476 5063
UVM_INFO @ 2507107480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78413105830924116710828501388952039227407047288612543949494041054427739237021 4798
UVM_INFO @ 16686256625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32397247784795824200954327034473567816783580566799810138699530402063574722520 10276
UVM_INFO @ 1689628762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12031000093108491547656520933255777076659199702589703008190200930955720295159 150
UVM_INFO @ 108432830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22623484597480181714827340365695966750189773372586489155198451743167773063339 1496
UVM_INFO @ 9552198458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3980711960032776883053460493138657799197597356522030422392029629055556059851 2447
UVM_INFO @ 21030869096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93991249772988234216688142767756781307048478591488078048975052599672756997856 202
UVM_INFO @ 227820426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103868458881036360321372669846586183744236760961503163479309858835407557459054 483
UVM_INFO @ 2702938279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54400922843966080433632021946374437004415741846690557365026876993831024993300 9886
UVM_INFO @ 3240022000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 915302595426663717279733090087687218733274835730476679872013129909171060252 304
UVM_INFO @ 304639343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14837174437112965355073186540818988073878863681736843563848131815119053253990 925
UVM_INFO @ 1728373945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53705365853439380119647159774620959457763032264946325948929408131082645569013 159
UVM_INFO @ 2195630010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93060632338145007502535189242199621573049064032957844152883504174611440581804 4844
UVM_INFO @ 10823862023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19691351157159808239631430459452975417853410526724247417138499005780790794398 1348
UVM_INFO @ 3446899413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57471770937631533535621282024801975338441011478247594780089557418710750821657 8149
UVM_INFO @ 3181309844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9615190908298344031748822874704316464290055005774843891323034522901443921609 12769
UVM_INFO @ 7189384133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100102247262033547245211613885857214845753015460781217250456657560193541563954 205
UVM_INFO @ 906145551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33572172018474037633998689482470175543550670250064314704524184448782820233355 151
UVM_INFO @ 1556145996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56203777806178519227258078669186823358891292114388395044120248014671012380849 151
UVM_INFO @ 598956610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 21573047523019914679403889671709356997999548786153225351383655258170238584604 3059
UVM_INFO @ 3365497573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105003537120999929947256349636290430823879131648243315597980487456291030631900 7247
UVM_INFO @ 15957976017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*
lc_ctrl_stress_all_with_rand_reset 107329354629577997767340711420195969471318760228865769016863258374469939799998 2710
UVM_INFO @ 1540331974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---