Simulation Results

Simulation Results: sram_ctrl/main

10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.67 %

code
95.76 %

assert
95.92 %

func
98.33 %

line
99.16 %

branch
98.14 %

cond
92.07 %

toggle
89.41 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		95.07%
V3		100.00%

205/205 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	91.390s	4251.366us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.030s	43.484us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.060s	40.064us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.730s	2131.146us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.130s	60.920us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	5.640s	371.047us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.060s	40.064us	20	20	100.00
	sram_ctrl_csr_aliasing	1.130s	60.920us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	398.110s	276959.576us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	175.270s	20924.446us	50	50	100.00

820/820 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1157.800s	25599.284us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	403.070s	5805.540us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	2572.600s	1503774.763us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1663.800s	87255.918us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	117.760s	17799.457us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1419.320s	40408.975us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	85.620s	4308.633us	50	50	100.00
	sram_ctrl_partial_access_b2b	529.130s	46383.454us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	105.960s	1866.029us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	104.660s	1599.115us	50	50	100.00
	sram_ctrl_throughput_w_readback	100.390s	1452.908us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1524.100s	35744.585us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	6.130s	4799.611us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	5217.180s	512136.426us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.070s	16.374us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	5.350s	536.308us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	5.350s	536.308us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	43.484us	5	5	100.00
	sram_ctrl_csr_rw	1.060s	40.064us	20	20	100.00
	sram_ctrl_csr_aliasing	1.130s	60.920us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.150s	66.223us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	43.484us	5	5	100.00
	sram_ctrl_csr_rw	1.060s	40.064us	20	20	100.00
	sram_ctrl_csr_aliasing	1.130s	60.920us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.150s	66.223us	20	20	100.00

V2S

347/365 passed

95.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	60.570s	33837.085us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00
	sram_ctrl_tl_intg_err	3.890s	4042.076us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.890s	4042.076us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1524.100s	35744.585us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1524.100s	35744.585us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.060s	40.064us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1419.320s	40408.975us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1419.320s	40408.975us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1419.320s	40408.975us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	117.760s	17799.457us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				43	50	86.00
	sram_ctrl_mubi_enc_err	12.170s	9551.013us	43	50	86.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	60.570s	33837.085us	20	20	100.00
sec_cm_mem_readback				44	50	88.00
	sram_ctrl_readback_err	11.500s	8224.171us	44	50	88.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	91.390s	4251.366us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	91.390s	4251.366us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1419.320s	40408.975us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	117.760s	17799.457us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	91.390s	4251.366us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.070s	99.361us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	205.640s	6894.667us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	38383342635077378087525446038312592411106000181718465010905323678499637728575	100	UVM_INFO @ 2553180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	1607664312281636283008911205810572165034663903548172261712044255091100160086	99	UVM_INFO @ 7074874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	34757911471738682217532292476281386520532960947537335834449776710488268464174	102	UVM_INFO @ 18128252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	11174264665096818251858217425076120815831059535367352589493713571628422422723	101	UVM_ERROR @ 99360842 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 99360842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	109861724816507825994430410648436694333254338714238275319586554399520984578261	101	UVM_ERROR @ 9781468 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 9781468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	110079811643705918078487771963940757985646379859833488951166325114637469493668	98	UVM_INFO @ 678222281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	25763640272835010730857769851865224783373181196569960998604942737593344267039	98	UVM_INFO @ 685981148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	85105766177123404618578680114868303903338953383731717311030128214269123438371	98	UVM_INFO @ 2740030874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	40026593766024941960499368552389832521165553834316207468543252214848304350415	98	UVM_INFO @ 824152494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	107768391976962633099767880893690425239197906481850223641071249391742502100252	98	UVM_INFO @ 2637789997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	43741090969173161090678482782679692805757116807567885026930833485593944132833	98	UVM_INFO @ 5051182582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	69986176753214975992077007406323978122801338326115034317756211952942428421263	104	UVM_ERROR @ 1103611422 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 1103611422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	32124932645314223725181303729091481480717011991889968081347146185316994212136	104	UVM_ERROR @ 1046508667 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 1046508667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	113328644482694255070287204208141290517371566258304776039322466761922101005481	104	UVM_ERROR @ 664445323 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 664445323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	82496684868771817209158969408941347955899533185679824840301974800902707052349	104	UVM_ERROR @ 2743529639 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 2743529639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	60441320381412055110741588695401856055411040322577997154432518073566708926599	104	UVM_ERROR @ 2676963805 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 2676963805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	86196088648337164237304012270829501714789472704206288074369124305209048150236	104	UVM_ERROR @ 664443928 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 664443928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	21697807876939797146869360097983018644275482259436231207373092222855843657664	104	UVM_ERROR @ 657600500 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 657600500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---