Simulation Results: sram_ctrl/ret

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.65 %
  • code
  • 95.73 %
  • assert
  • 95.88 %
  • func
  • 98.33 %
  • line
  • 99.13 %
  • branch
  • 98.10 %
  • cond
  • 92.07 %
  • toggle
  • 89.35 %
  • FSM
  • 100.00 %
Validation stages
V1
99.51%
V2
100.00%
V2S
94.79%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 104.440s 2856.677us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 14.482us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.050s 55.898us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.550s 688.358us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.150s 48.960us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.450s 77.186us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.050s 55.898us 20 20 100.00
sram_ctrl_csr_aliasing 1.150s 48.960us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 16.160s 9317.262us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 6.880s 307.249us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1167.800s 29128.818us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 329.560s 17523.834us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 99.450s 18804.314us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1244.910s 5206.609us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 12.520s 914.799us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1401.800s 14659.020us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 114.830s 3202.920us 50 50 100.00
sram_ctrl_partial_access_b2b 579.780s 24278.900us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 111.250s 538.765us 50 50 100.00
sram_ctrl_throughput_w_partial_write 94.940s 588.806us 50 50 100.00
sram_ctrl_throughput_w_readback 104.090s 330.176us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1307.860s 20621.760us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.250s 52.217us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 4787.840s 20825.962us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.060s 20.540us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.920s 2038.917us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.920s 2038.917us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 14.482us 5 5 100.00
sram_ctrl_csr_rw 1.050s 55.898us 20 20 100.00
sram_ctrl_csr_aliasing 1.150s 48.960us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.260s 243.934us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 14.482us 5 5 100.00
sram_ctrl_csr_rw 1.050s 55.898us 20 20 100.00
sram_ctrl_csr_aliasing 1.150s 48.960us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.260s 243.934us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.550s 7336.051us 20 20 100.00
tl_intg_err 19 25 76.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
sram_ctrl_tl_intg_err 3.520s 604.256us 19 20 95.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
sec_cm_bus_integrity 19 20 95.00
sram_ctrl_tl_intg_err 3.520s 604.256us 19 20 95.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1307.860s 20621.760us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1307.860s 20621.760us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.050s 55.898us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1401.800s 14659.020us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1401.800s 14659.020us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1401.800s 14659.020us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 12.520s 914.799us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 47 50 94.00
sram_ctrl_mubi_enc_err 1.660s 415.380us 47 50 94.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.550s 7336.051us 20 20 100.00
sec_cm_mem_readback 40 50 80.00
sram_ctrl_readback_err 1.490s 42.572us 40 50 80.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 104.440s 2856.677us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 104.440s 2856.677us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1401.800s 14659.020us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 12.520s 914.799us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 104.440s 2856.677us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.100s 9.515us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
sram_ctrl_stress_all_with_rand_reset 893.740s 28824.196us 48 50 96.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 110162799094117330752598172027075793141981627184763206534388756527656803491873 99
UVM_INFO @ 10606766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 30862860749438779908608064697140121990595846925997282677708309669734999189413 99
UVM_INFO @ 4573229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 20144124816754410939434547022619734134027806067752342528872403652855671816501 100
UVM_INFO @ 7205007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 32981306544459518753407121222735070085046811657076049667071662311797117499018 101
UVM_ERROR @ 7544803 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 7544803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 30113063233427993909363178592299610036936818012713234767992013564002923239126 105
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 8656652ps failed at 8656652ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 8667178ps failed at 8667178ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 10295397934518523048650522755677001751749527171300858757726518820914553386839 98
UVM_INFO @ 27537980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 65194248053744531904425055615498859018064103113324491171712164335565220806394 98
UVM_INFO @ 23933079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 71593912777622958156013554103654038768767575142066992108514932782509807699900 98
UVM_INFO @ 47951441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36677738913719759449459565865812803829934262344587233588644510688257717339372 98
UVM_INFO @ 26998324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 215359861220875269830438950610563757305807688943918389949875045806742770481 98
UVM_INFO @ 156322150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 102920733221039624051733403101166996197728608534354969615985421816758405311730 98
UVM_INFO @ 51780867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 67545284777134179145321930465652390085741295881699050513115970271365067502040 98
UVM_INFO @ 36673556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 20609670021370523772102797365868820659448791972108430943615796269428219038079 98
UVM_INFO @ 31446687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
sram_ctrl_tl_intg_err 20006481436717952436886323955768903039648707471494737844576907796231962880889 237
UVM_INFO @ 95758238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 47717509711128335430928159967610223657230229032692945121964282358465959386451 104
UVM_ERROR @ 45281814 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 45281814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 78297435153423746344435186538047150880570365708196421484982515893054730935608 104
UVM_ERROR @ 26992540 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 26992540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 78985855288704813820122269324372098475963687980643042180713479830423812199305 104
UVM_ERROR @ 143382506 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 143382506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 11018608518103342429403624249908693435546144537408204500013059277079679033876 245
UVM_INFO @ 914129213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_stress_all_with_rand_reset 86813835034254683656740649484307536189387584795291978808513471469953094344429 125
UVM_INFO @ 4035219941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 25400079050833671156976106955265270784737387493560991801662398220128418109543 98
UVM_INFO @ 169078790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *).
sram_ctrl_readback_err 111897200786758135374430734452220414207833988465734469698756981680745263626517 98
TL item was: req: (cip_tl_seq_item@2933) { a_addr: 'hf03f1698 a_data: 'hc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h1 a_user: 'h2617f d_param: 'h0 d_source: 'h28 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 80645755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 76950519436863155007634969707791905528473708500909193073068046757954586775447 98
TL item was: req: (cip_tl_seq_item@3465) { a_addr: 'h57e02248 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h42 a_opcode: 'h4 a_user: 'h24baa d_param: 'h0 d_source: 'h42 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 24600093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---