Simulation Results: edn/edn0

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.42 %
  • code
  • 95.80 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.17 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.340s 19.689us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.150s 57.257us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.180s 13.789us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 5.250s 1009.554us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.550s 63.852us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.470s 72.686us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.180s 13.789us 20 20 100.00
edn_csr_aliasing 1.550s 63.852us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 75.230s 4579.503us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 75.230s 4579.503us 300 300 100.00
genbits 300 300 100.00
edn_genbits 75.230s 4579.503us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.430s 27.355us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.650s 30.143us 200 200 100.00
errs 100 100 100.00
edn_err 1.510s 19.001us 100 100 100.00
disable 92 100 92.00
edn_disable 1.280s 20.141us 50 50 100.00
edn_disable_auto_req_mode 8.050s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 6.540s 322.891us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.050s 16.996us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 2.420s 190.076us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.450s 548.275us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.450s 548.275us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.150s 57.257us 5 5 100.00
edn_csr_rw 1.180s 13.789us 20 20 100.00
edn_csr_aliasing 1.550s 63.852us 5 5 100.00
edn_same_csr_outstanding 1.720s 149.092us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.150s 57.257us 5 5 100.00
edn_csr_rw 1.180s 13.789us 20 20 100.00
edn_csr_aliasing 1.550s 63.852us 5 5 100.00
edn_same_csr_outstanding 1.720s 149.092us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.510s 141.054us 20 20 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.970s 22.542us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.650s 30.143us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.650s 30.143us 200 200 100.00
edn_sec_cm 6.210s 794.508us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.650s 30.143us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.510s 141.054us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 40 50 80.00
edn_stress_all_with_rand_reset 95.620s 4546.109us 40 50 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 54723173022805179836133758411150161521660844614023248277028721715876821702568 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 3853480028324721388233095588115054184113319771629737406621592944953905676881 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92622044218335484038491367918795366538568373401557045109953205215070299087691 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111702294025959097649943793549025412129633398606092422490777690961414181163279 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111870433923478873105757986504922950740181446381015475288732623305629386560802 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 53324354534284680296350553281958005816679748826575463111631184475940369197876 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 28473958006852211253816675395602915632369327855652944722472386226626911121469 144
UVM_ERROR @ 1011405002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1011405002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 30436328590391562316665285004462197792904911426362033911344685595272683736297 358
UVM_ERROR @ 4546109344 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4546109344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 20340068351827709863790659585505111686822888507065664708652788078585714503537 280
UVM_ERROR @ 2379241878 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2379241878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 9054328905227000106515418215422189276272530946593986797380727430234001408419 276
UVM_ERROR @ 1877226376 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1877226376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 83551878075579464622217812636913124957135041955231453451293214132857028990331 368
UVM_ERROR @ 3284398252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3284398252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91114612378462478713610740772687341937374032683013318657235016601452643063936 183
UVM_ERROR @ 570348041 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 570348041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 21170685834616627711888229674567238412325729337712279895609400615693184156876 249
UVM_ERROR @ 3403182206 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3403182206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41862115694692879259498459790333523047899600045220334839544104477646495668575 192
UVM_ERROR @ 1079965310 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1079965310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 38827588022962488808848872980471629490343367768122236919478096634553841233490 237
UVM_ERROR @ 1438362172 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1438362172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 52459497015592339561748651414530755720330598367737183964090083774659656544681 116
UVM_ERROR @ 114934780 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114934780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 1053368176939720058656145584096393635205835773023917975225382663963497787296 88
UVM_FATAL @ 103232945 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00467662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 103232945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110787334874366706673948370618262836920884510126662507765628502209036664254716 88
UVM_FATAL @ 12898656 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000016a3 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 12898656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---