Simulation Results: edn/edn1

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 96.16 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
94.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.290s 32.497us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.290s 20.772us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.260s 15.924us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 6.440s 257.733us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.430s 124.618us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.480s 35.103us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.260s 15.924us 20 20 100.00
edn_csr_aliasing 1.430s 124.618us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 62.280s 5355.366us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 62.280s 5355.366us 300 300 100.00
genbits 300 300 100.00
edn_genbits 62.280s 5355.366us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.550s 21.237us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.590s 104.718us 200 200 100.00
errs 100 100 100.00
edn_err 1.490s 28.494us 100 100 100.00
disable 92 100 92.00
edn_disable 1.220s 12.619us 50 50 100.00
edn_disable_auto_req_mode 3.560s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 5.970s 652.223us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.220s 53.791us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.630s 91.679us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.810s 278.353us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.810s 278.353us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.290s 20.772us 5 5 100.00
edn_csr_rw 1.260s 15.924us 20 20 100.00
edn_csr_aliasing 1.430s 124.618us 5 5 100.00
edn_same_csr_outstanding 1.660s 86.151us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.290s 20.772us 5 5 100.00
edn_csr_rw 1.260s 15.924us 20 20 100.00
edn_csr_aliasing 1.430s 124.618us 5 5 100.00
edn_same_csr_outstanding 1.660s 86.151us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.080s 114.910us 20 20 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.220s 47.652us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.590s 104.718us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.590s 104.718us 200 200 100.00
edn_sec_cm 5.240s 378.127us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.590s 104.718us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.080s 114.910us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 47 50 94.00
edn_stress_all_with_rand_reset 102.940s 59334.010us 47 50 94.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 43085873589700221833180836270578259177379387577513990782149209440277713146986 88
UVM_FATAL @ 31713898 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000942 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 31713898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 36524648510998608003467294791100690991480871470865846571222226816373112090630 88
UVM_FATAL @ 27782741 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00a17692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 27782741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34027917569816125288040184374147195428277834735850097016394249919574891419689 88
UVM_FATAL @ 59780511 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 59780511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 61997662186984490872243931936984250836011548569362808728032364084525315634981 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2451698408848147827371052270295125137166988652884123063024773128124120462478 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 67439908057761710641427542664117676895210644940072714620600670011159513482101 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 30616863052408740294588914428411874517382451011904598887161628459587854430033 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 93824034984157725889354940335766429524760324657804199635107812084312714877970 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 1281635173386922386256819811994887439986030640755632540815695161349454220483 194
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1195138957 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 94877102008331427482490880345716708205169232593419905987379526820306948779335 252
UVM_ERROR @ 1954838162 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1954838162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 6774848685158810511186623507682006769048265268023552906629129812742425185657 299
UVM_ERROR @ 3094155092 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3094155092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---