Simulation Results: keymgr

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 98.47 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.12 %
  • toggle
  • 98.51 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.61%
V2S
99.74%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 16.220s 2890.124us 50 50 100.00
random 50 50 100.00
keymgr_random 46.800s 5490.186us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 2.200s 59.170us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 20.570s 8612.357us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 8.930s 479.458us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.050s 227.244us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_csr_aliasing 8.930s 479.458us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 80.770s 1985.260us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 31.880s 1403.335us 50 50 100.00
keymgr_sideload_kmac 35.520s 2699.460us 50 50 100.00
keymgr_sideload_aes 45.260s 2420.958us 50 50 100.00
keymgr_sideload_otbn 40.310s 3159.351us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 29.700s 4078.141us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 18.970s 9702.986us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 5.760s 436.773us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 66.670s 36378.310us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 7.200s 1356.745us 50 50 100.00
sync_async_fault_cross 48 50 96.00
keymgr_sync_async_fault_cross 10.560s 936.606us 48 50 96.00
stress_all 50 50 100.00
keymgr_stress_all 366.160s 53484.324us 50 50 100.00
intr_test 50 50 100.00
keymgr_intr_test 1.520s 17.741us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 2.040s 237.990us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.020s 748.812us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.020s 748.812us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 2.200s 59.170us 5 5 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_csr_aliasing 8.930s 479.458us 5 5 100.00
keymgr_same_csr_outstanding 4.370s 1207.071us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 2.200s 59.170us 5 5 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_csr_aliasing 8.930s 479.458us 5 5 100.00
keymgr_same_csr_outstanding 4.370s 1207.071us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 7.490s 806.083us 20 20 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 3.890s 394.872us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 3.890s 394.872us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 3.890s 394.872us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 3.890s 394.872us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.080s 5999.200us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.490s 806.083us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 3.890s 394.872us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 80.770s 1985.260us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_random 46.800s 5490.186us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_random 46.800s 5490.186us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.760s 54.979us 20 20 100.00
keymgr_random 46.800s 5490.186us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 18.970s 9702.986us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 7.200s 1356.745us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 7.200s 1356.745us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 46.800s 5490.186us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 11.930s 1523.768us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 27.780s 5848.521us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 18.970s 9702.986us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.780s 5848.521us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.780s 5848.521us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.780s 5848.521us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.330s 883.698us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 27.780s 5848.521us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
keymgr_stress_all_with_rand_reset 24.840s 2023.371us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 30044459435221433034956982469441499854941851409974113710293733384968011250179 299
UVM_ERROR @ 1281472674 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1281472674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 10118708459988680437292054249880427326629391142459238410368679337729913296764 249
UVM_ERROR @ 294690133 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 294690133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87944773716015252787487317456818318581857210404013083654385791159224366625428 670
UVM_ERROR @ 171294630 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 171294630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 88677566582053769200847770367823619779080644978094045070774532292813614021174 703
UVM_ERROR @ 760404550 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 760404550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25777009707427548292856254167372257698492192298167522345103891778288421942087 382
UVM_ERROR @ 629993909 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 629993909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95234901996485053342312947408608571252968815286615510664532576269332314429852 428
UVM_ERROR @ 203251854 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 203251854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 36750278274571983758287598857599589044032075059832781683390713624367267281720 97
UVM_ERROR @ 515750099 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 515750099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 4229394739134591150280403291836821764246480656082130749025310834342324379167 355
UVM_ERROR @ 136954107 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 136954107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68415055566447186981955394746610546265313187076699175998804573919362670978945 643
UVM_ERROR @ 334178409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 334178409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 84997887625434796781257510551899216699873669648570324641850519548105162537646 425
UVM_ERROR @ 200653823 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 200653823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 16614301045073868217138802937269449891408823966826593772919531242734173834219 107
UVM_ERROR @ 620686059 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 620686059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 41460111044352818360535834575079529618838198789990539515244401570211748514364 378
UVM_ERROR @ 212852099 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 212852099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 89272809884734303333901029995861611553655040122147022570475516155198245149295 394
UVM_ERROR @ 143138732 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 143138732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 29250497088368922630887481007199107202960106445156184443500098831894774600553 144
UVM_ERROR @ 219026913 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 219026913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100019891770812365505144422641023011465209149089037038690431649870942245243962 191
UVM_ERROR @ 465768950 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 465768950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25742546069813934849948604899420627308527023473627779716329597654193475509478 162
UVM_ERROR @ 121160391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 121160391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 16007030576086380333687143896749144414036218816508671709708320302901289481077 406
UVM_ERROR @ 486996592 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 486996592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 104813376999224355584865595432820653210654532569570913219903921599693649234418 302
UVM_ERROR @ 523420917 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 523420917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87812580750343742127827903085083534488047716540272645384191829113676751382136 1471
UVM_ERROR @ 1616097968 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1616097968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78209818295447013327646475365055545797414162202029896345906213897684497727222 333
UVM_ERROR @ 162153008 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 162153008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19075304215433077359851652121380540019604163309153847698474941084167178677567 209
UVM_ERROR @ 421911880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 421911880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 65511925785822228251347003118225243730758716483844232348816829415222187625113 161
UVM_ERROR @ 107238709 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 107238709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sync_async_fault_cross 40615269923946688899206352222013604098200911952077512284564013141388127805270 155
UVM_ERROR @ 77032132 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 77032132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes
keymgr_lc_disable 51366275674912512458571287262635098623831868311973879463525160519507213217904 314
UVM_ERROR @ 1486507919 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6425430764999401232515082186741839513596077565902696240588568277270346073921804190963066557793347137058722383038475995749158386444232711318956388769982426 [0x7aaed9f2384eff231d8eb7247ad9649199a44cef0ec548a29ecb01f131ed943eac5297ca417ebcd3821b405d2352778f6f83fd3830a9850a6476feeb7f35e7da] vs 6425430764999401232515082186741839513596077565902696240588568277270346073921804190963066557793347137058722383038475995749158386444232711318956388769982426 [0x7aaed9f2384eff231d8eb7247ad9649199a44cef0ec548a29ecb01f131ed943eac5297ca417ebcd3821b405d2352778f6f83fd3830a9850a6476feeb7f35e7da]) AES key at state StOwnerIntKey for Sealing Aes
UVM_INFO @ 1486507919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---