Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.72 %
  • code
  • 88.62 %
  • assert
  • 96.13 %
  • func
  • 96.40 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.30 %
  • toggle
  • 91.35 %
  • FSM
  • 74.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.72%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.990s 137.903us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.350s 25.139us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.440s 18.077us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.960s 224.635us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.760s 60.161us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.170s 53.124us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.440s 18.077us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 60.161us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.460s 138.523us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.970s 1483.307us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.300s 14.051us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.380s 109.553us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 16.160s 5840.849us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_prog_failure 4.380s 109.553us 50 50 100.00
lc_ctrl_errors 16.160s 5840.849us 50 50 100.00
lc_ctrl_security_escalation 11.880s 615.922us 50 50 100.00
lc_ctrl_jtag_state_failure 74.450s 15661.523us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.720s 6499.995us 20 20 100.00
lc_ctrl_jtag_errors 87.140s 5039.531us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 4.970s 1078.089us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.940s 65.108us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.140s 1648.617us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 21.730s 1318.350us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 53.693us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.600s 282.349us 10 10 100.00
lc_ctrl_jtag_alert_test 2.020s 364.479us 10 10 100.00
lc_ctrl_jtag_smoke 13.280s 2194.787us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.210s 2477.837us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.720s 6499.995us 20 20 100.00
lc_ctrl_jtag_errors 87.140s 5039.531us 20 20 100.00
lc_ctrl_jtag_access 22.560s 1298.599us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.690s 3838.049us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 32.290s 6890.025us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.550s 16.495us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 439.550s 19043.342us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.890s 32.610us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.050s 131.918us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.050s 131.918us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.350s 25.139us 5 5 100.00
lc_ctrl_csr_rw 1.440s 18.077us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 60.161us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.870s 90.274us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.350s 25.139us 5 5 100.00
lc_ctrl_csr_rw 1.440s 18.077us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 60.161us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.870s 90.274us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.120s 119.375us 20 20 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.120s 119.375us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.970s 1483.307us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.730s 1045.605us 50 50 100.00
lc_ctrl_sec_cm 10.300s 239.649us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.880s 615.922us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.460s 138.523us 50 50 100.00
lc_ctrl_jtag_state_post_trans 23.210s 2477.837us 20 20 100.00
sec_cm_intersig_mubi 49 50 98.00
lc_ctrl_sec_mubi 19.530s 1046.659us 49 50 98.00
sec_cm_token_valid_ctrl_mubi 49 50 98.00
lc_ctrl_sec_mubi 19.530s 1046.659us 49 50 98.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.950s 971.184us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.570s 486.980us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.570s 486.980us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 50 40.00
lc_ctrl_stress_all_with_rand_reset 113.840s 20934.141us 20 50 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 91430502977630848157024686872599641759562257342687400230841112761184878922639 3926
UVM_ERROR @ 7587040180 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7587040180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70047641407704559264615905575408245284124770076602259025399459300622595431560 6137
UVM_ERROR @ 3379641763 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3379641763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75756368859244931409703332269775789850432667874798405621123401793500596168679 8426
UVM_ERROR @ 2876720393 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2876720393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61607114657530654683767359216605965212944994486902229628404781304412018948573 264
UVM_ERROR @ 2173342644 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2173342644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91183275763803951907832129695267250823386059090916289244352836864199302171032 150
UVM_ERROR @ 106164343 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106164343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25495419728051245334906175665591028834939390061007429585799845666173276907536 739
UVM_ERROR @ 1610323765 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1610323765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33711990817289473221185393022522091458295308993894788496700965281591589151195 956
UVM_ERROR @ 1055642699 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1055642699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7068873255419760840940807481383486466117194029878518163091875572851127894691 4039
UVM_ERROR @ 7775069669 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7775069669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19433163696738357742125541856474779801970467963785048678956307701585800912996 209
UVM_ERROR @ 449043892 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 449043892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105997176819511791514548228475332393807815058378018453765425864294043628166198 10622
UVM_ERROR @ 1650814466 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1650814466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39892144659076922664659682263206692543074955023079829998728948495113934938090 3374
UVM_ERROR @ 5687458059 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5687458059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87794290560747854422483039258594190296795267986098556007343129994698999226070 1194
UVM_ERROR @ 5042965519 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5042965519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43843224989314932043022744223573939589536336733420564467814903768324806431239 8451
UVM_ERROR @ 7978554854 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7978554854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75999719059048742958047392348393859707986276971148511703126924949105840857972 579
UVM_ERROR @ 7595389821 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7595389821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96934721480376393950554693729001847324414147718055834506624378786537008619808 540
UVM_ERROR @ 526197516 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 526197516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56742544636989744050139257475779614428649764832814149324478384664182597100630 2059
UVM_ERROR @ 1996137522 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1996137522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 4624473972324308995677977614850106161552594508649388698277196710707628591808 150
UVM_ERROR @ 217203622 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217203622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45247019058389205543136422499468643611129846366437131893386688842253150281354 354
UVM_ERROR @ 1704799376 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1704799376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101542077134726850025760277242652721496305933610269991368726184803811666055976 3209
UVM_ERROR @ 858824010 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 858824010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71497086626875403114155209122919481004440416024523516279884878127645988001150 194
UVM_ERROR @ 396660085 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 396660085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64711886780144680220077957859827423531378138661133349416389981611819932842329 488
UVM_ERROR @ 4621590653 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4621590653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7914139641446708995448712205508978582500962644892912161308515788421292915848 746
UVM_ERROR @ 501573824 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 501573824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105785393574942487506002752279649316543136470126229146364884902362280924350193 4760
UVM_ERROR @ 4814756494 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4814756494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 36251177672648657140786283617413274461051370021158007709922714233279668287121 201
UVM_ERROR @ 251814238 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 251814238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82032593459700210788858052349738298817432058809933914413908263967069787691403 1595
UVM_ERROR @ 2523593734 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2523593734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18700119536972012203491354033370666082660602493926051536683649485035059379061 209
UVM_ERROR @ 278505229 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 278505229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39781448152673103870012576557501555950263203841370910998367934180696408990488 4238
UVM_ERROR @ 996960122 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 996960122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28770895104888522914444497863156646740431877495878709587093771015385848183800 3912
UVM_ERROR @ 2410029441 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2410029441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103427011337040109728284346996541796073960249336086816068265534386693561768502 8315
UVM_ERROR @ 10278314496 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10278314496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_sec_mubi 37891250924013518755264923476472065109198660528095901242994290230802685684290 2764
UVM_ERROR @ 211202895 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 211202895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 51360195205191416918734122615757862618274431703032466120542826272344894465749 5467
UVM_ERROR @ 9954470346 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 9954470346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---