Simulation Results: rv_dm/use_dmi_interface

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 75.51 %
  • assert
  • 96.32 %
  • func
  • 85.09 %
  • line
  • 91.16 %
  • branch
  • 77.56 %
  • cond
  • 78.69 %
  • toggle
  • 73.89 %
  • FSM
  • 56.25 %
Validation stages
V1
98.89%
V2
53.36%
V2S
93.33%
V3
30.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rv_dm_smoke 4.910s 2775.936us 2 2 100.00
jtag_dtm_csr_hw_reset 5 5 100.00
rv_dm_jtag_dtm_csr_hw_reset 4.350s 811.862us 5 5 100.00
jtag_dtm_csr_rw 20 20 100.00
rv_dm_jtag_dtm_csr_rw 3.590s 702.435us 20 20 100.00
jtag_dtm_csr_bit_bash 5 5 100.00
rv_dm_jtag_dtm_csr_bit_bash 42.470s 11423.311us 5 5 100.00
jtag_dtm_csr_aliasing 5 5 100.00
rv_dm_jtag_dtm_csr_aliasing 4.290s 2272.306us 5 5 100.00
jtag_dmi_csr_hw_reset 5 5 100.00
rv_dm_jtag_dmi_csr_hw_reset 35.400s 8490.056us 5 5 100.00
jtag_dmi_csr_rw 20 20 100.00
rv_dm_jtag_dmi_csr_rw 46.070s 16615.090us 20 20 100.00
jtag_dmi_csr_bit_bash 20 20 100.00
rv_dm_jtag_dmi_csr_bit_bash 194.230s 91229.702us 20 20 100.00
jtag_dmi_csr_aliasing 5 5 100.00
rv_dm_jtag_dmi_csr_aliasing 408.800s 178286.161us 5 5 100.00
jtag_dmi_cmderr_busy 2 2 100.00
rv_dm_cmderr_busy 2.150s 317.327us 2 2 100.00
jtag_dmi_cmderr_not_supported 2 2 100.00
rv_dm_cmderr_not_supported 3.690s 1076.285us 2 2 100.00
cmderr_exception 2 2 100.00
rv_dm_cmderr_exception 2.720s 372.782us 2 2 100.00
mem_tl_access_resuming 0 2 0.00
rv_dm_mem_tl_access_resuming 1.220s 60.715us 0 2 0.00
mem_tl_access_halted 2 2 100.00
rv_dm_mem_tl_access_halted 1.540s 577.892us 2 2 100.00
cmderr_halt_resume 2 2 100.00
rv_dm_cmderr_halt_resume 3.260s 585.428us 2 2 100.00
dataaddr_rw_access 2 2 100.00
rv_dm_dataaddr_rw_access 1.600s 365.276us 2 2 100.00
halt_resume 8 8 100.00
rv_dm_halt_resume_whereto 4.330s 826.649us 8 8 100.00
progbuf_busy 2 2 100.00
rv_dm_cmderr_busy 2.150s 317.327us 2 2 100.00
abstractcmd_status 2 2 100.00
rv_dm_abstractcmd_status 1.740s 312.037us 2 2 100.00
progbuf_read_write_execute 2 2 100.00
rv_dm_progbuf_read_write_execute 1.700s 713.457us 2 2 100.00
progbuf_exception 2 2 100.00
rv_dm_cmderr_exception 2.720s 372.782us 2 2 100.00
rom_read_access 2 2 100.00
rv_dm_rom_read_access 1.110s 45.563us 2 2 100.00
csr_hw_reset 5 5 100.00
rv_dm_csr_hw_reset 3.490s 519.940us 5 5 100.00
csr_rw 20 20 100.00
rv_dm_csr_rw 2.950s 114.187us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_dm_csr_bit_bash 65.540s 7446.971us 5 5 100.00
csr_aliasing 5 5 100.00
rv_dm_csr_aliasing 63.070s 13801.113us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_dm_csr_mem_rw_with_rand_reset 4.150s 238.718us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_dm_csr_aliasing 63.070s 13801.113us 5 5 100.00
rv_dm_csr_rw 2.950s 114.187us 20 20 100.00
mem_walk 5 5 100.00
rv_dm_mem_walk 1.300s 79.208us 5 5 100.00
mem_partial_access 5 5 100.00
rv_dm_mem_partial_access 1.210s 54.238us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 2 2 100.00
rv_dm_smoke 4.910s 2775.936us 2 2 100.00
jtag_dtm_hard_reset 2 2 100.00
rv_dm_jtag_dtm_hard_reset 1.110s 170.163us 2 2 100.00
jtag_dtm_idle_hint 2 2 100.00
rv_dm_jtag_dtm_idle_hint 1.700s 531.439us 2 2 100.00
jtag_dmi_failed_op 2 2 100.00
rv_dm_dmi_failed_op 1.390s 274.171us 2 2 100.00
jtag_dmi_dm_inactive 2 2 100.00
rv_dm_jtag_dmi_dm_inactive 3.120s 1019.609us 2 2 100.00
sba 0 40 0.00
rv_dm_sba_tl_access 806.640s 300000.000us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 839.350s 300000.000us 0 20 0.00
bad_sba 0 20 0.00
rv_dm_bad_sba_tl_access 770.840s 300000.000us 0 20 0.00
sba_autoincrement 0 20 0.00
rv_dm_autoincr_sba_tl_access 796.270s 300000.000us 0 20 0.00
jtag_dmi_debug_disabled 0 2 0.00
rv_dm_jtag_dmi_debug_disabled 1.510s 207.337us 0 2 0.00
sba_debug_disabled 2 2 100.00
rv_dm_sba_debug_disabled 1.820s 1230.595us 2 2 100.00
ndmreset_req 2 2 100.00
rv_dm_ndmreset_req 2.120s 466.774us 2 2 100.00
hart_unavail 0 5 0.00
rv_dm_hart_unavail 1.330s 102.254us 0 5 0.00
tap_ctrl_transitions 11 11 100.00
rv_dm_tap_fsm 21.580s 6833.502us 1 1 100.00
rv_dm_tap_fsm_rand_reset 98.780s 8414.104us 10 10 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.030s 90.191us 1 1 100.00
stress_all 5 50 10.00
rv_dm_stress_all 7884.550s 10000000.000us 5 50 10.00
alert_test 50 50 100.00
rv_dm_alert_test 1.720s 168.700us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_dm_tl_errors 7.150s 1099.799us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_dm_tl_errors 7.150s 1099.799us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_dm_csr_aliasing 63.070s 13801.113us 5 5 100.00
rv_dm_csr_hw_reset 3.490s 519.940us 5 5 100.00
rv_dm_csr_rw 2.950s 114.187us 20 20 100.00
rv_dm_same_csr_outstanding 8.340s 433.204us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_dm_csr_aliasing 63.070s 13801.113us 5 5 100.00
rv_dm_csr_hw_reset 3.490s 519.940us 5 5 100.00
rv_dm_csr_rw 2.950s 114.187us 20 20 100.00
rv_dm_same_csr_outstanding 8.340s 433.204us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_dm_sec_cm 7.550s 1382.301us 5 5 100.00
rv_dm_tl_intg_err 27.550s 6405.523us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_dm_tl_intg_err 27.550s 6405.523us 20 20 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 4 4 100.00
rv_dm_sba_debug_disabled 1.820s 1230.595us 2 2 100.00
rv_dm_debug_disabled 1.210s 36.022us 2 2 100.00
sec_cm_lc_dft_en_intersig_mubi 4 4 100.00
rv_dm_sba_debug_disabled 1.820s 1230.595us 2 2 100.00
rv_dm_debug_disabled 1.210s 36.022us 2 2 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 2 2 100.00
rv_dm_smoke 4.910s 2775.936us 2 2 100.00
sec_cm_dm_en_ctrl_lc_gated 7 10 70.00
rv_dm_buffered_enable 3.420s 511.811us 7 10 70.00
sec_cm_sba_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.470s 144.295us 4 4 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.470s 144.295us 4 4 100.00
sec_cm_exec_ctrl_mubi 7 10 70.00
rv_dm_buffered_enable 3.420s 511.811us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
rv_dm_stress_all_with_rand_reset 57.460s 5922.880us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 543.460s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 75868643479381901969204153313871164247906351852764779758367169615925842772646 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 42449748279269327681562108492881738791611341018379197877601465142990090288803 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 91320999580164969400650396962515874382644542397335032972639536007493050904573 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 57933225460273252776835760230118714470449392447231591353726131092174522721592 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 22297767903869058523791800070400913658105833735929527511294211294222762245790 77
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 93640099351059853547274895857972068870400022086874386612307090410048177210505 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 24632698818384861973363331344456213771713665680477547714956746641146096014897 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 13852289749145768984907021840460217710151934063838428197476493595840130782583 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 14175881663261105433783036204719897544453340658326477935452992840379734565617 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 28846489255940144235762982506408954275280991049769366758378034466806126638509 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 39429390060443932173859452565063250890494881048006157340018082756852133263586 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 2271133973957468971116137670414236609212580460713311204578119204635018229183 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 33178410251420167192571392111774645784046346110104012202913843161109759450658 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 72198189047151166661065481878280400701213384650656463619223395081334363999937 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 6135428344291152288354965173081831243924777933205243719422679839601429173402 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 24024986032064581979847673090723208312293774731805336039891660974025422121695 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 78778997279108450162988268558069742280937666383771504993268569951585769945398 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 40551711522715669416342398311480847878371927286983579562639879831473097646138 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 98284470295480707272976588465818434629704933131289520852337918427464564782308 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 69106159511940227564240494189868629901884148889593859897999946123926516181488 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 81762302771590592117905368947027362828544930076651692589695729606638891181194 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 35329742122940991513590647947286331793816726936305416827807673169872363080502 80
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 81743456986618713780014822668792577435869027946641908822853635385629432707084 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 12739363929760666539312667224999580676291016874147574275198064064445021760947 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 93225352117343403943861594272061233107532284648377165381546029686163952570717 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 27090608081332301592737767271541719700015719524310172343320471221397502727401 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 114538849385562686339252233896271011030301835668337967772667562069104958594057 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 40570912067477328550705030405622509925174600768663818812629878635591766002865 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 61335188880681338193457884968796517440128995530412223660503455626031138247649 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 24540154057093223132086469190759297475493980665582482992999347993731187128704 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 44281194699439329662409473556875419271942045739579595864405544450662816143701 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 92499775994499358105103643638420869663689058073789198033839119734466564885432 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 46922332097828574537432549507974642298985973167975548614164259840684476019990 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 61008423189685344731435773032757528592425978119663885895735643838527339828530 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 101316415613452189215580549030351086201351689433659691996948555890606894806935 80
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 94219845904324566824564272060606163917294783710661622269699573050526838356517 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 103374736112878556005438864688432656337725700816734045323447499866605050738964 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 6566706515566388557137140834407735797538029306679257282546884995351063567225 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 84236062969298125560343563788311376389501968919703751560608484810159509067725 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 72536581755538307833193867544333730228716517203019516540860039838017015050962 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 13537242985549094487646477785678997455548870614150612856699103411647385461972 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 54439991810948283104831582062490928760912265716915359821516015718763853180200 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 98282894671130458741534666017822299237554713811775769288383423798588234894363 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 35712352676022078272406840188983795875567637004188351459174229396285684969771 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 21340688000530903839922293171074076292230218185444554385006144800716258992805 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 76537274647144097427042902787218365937419984776645930052729093705831126203211 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 112590576525807681414513292679591913395286955216735885145586315791747173866944 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 67199746083409303635428148982577423277669026869912658007868532861606144300800 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 27474850627798316607197999522881352338642425529417075801524200675814651611171 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 86796958081609470532201136168500263706214441074193470981534485140927787805991 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 82473529267413263736861522926140091710998652621662134260389817000779709397583 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 52560539265608035012228966668092120526868645092896490215106117940922511295059 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 1737072306082133786648761858170311392556524994401223419784276293606413747508 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 13939851201434965816888707123304383015715518394265578224189144245679676278883 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 33813087930466849196066083563054506746995560943553172287533663319005099897285 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 70483142076561987150782891331593355627100298019262110528092500817804539530882 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 51467901661476264806463763852150890529224808459438096309648153427286408973076 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 69452020043870021322980018335999666427018235620294038434807372310538363193827 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 41102264629772110564381741358765742905985326107466084496315524492751866723122 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 89699912302714501626049203606717144968683088542271008301758146086230119954787 78
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 70855857602459399324533047976876861979419252488794901494148702405184876489426 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 32103461340392862753690227966859671533852132738823558732633328581773227892848 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 46485513223530910451293661329494761988318287400260621222191789942908730182096 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 86347063789460807379328128793391211399795682767847174934750030791224072213490 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 85079736621804591290399764914771627645162496327911683252241949659646591353585 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 73780344069498773594887316234254029040443888265631028146662256265555424056101 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 91971814019711866778035683992783935566926208742379583938207425916566160065014 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 28303985926803347982381965517856905670113288768551847014115363544039585190914 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 4173007596941721202263242288252120419364898489500540050163825572536298041658 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 65660331138218915567816438451049062805032663852648192426649443954913881310383 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 70735085637088843617252875031835564958375843451373659911661297494638685654067 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 29208067722719494489317513855315979590884211378091854436188896409341952618450 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 100580528256054871496151519931384864855114087431450765650131279435862433125527 78
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 83456390894392416318782340327702513656883522871268213280593188147648513195736 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 76936815413027051268095617776953285133051439316861334795883715764089964600146 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 5473473291997212364690738478638241697318829786226078446842332203482000167899 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 54286315885707215044596535267178188003387690598942020265841523599684835762858 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 87128912106444103201603272959843484071614922722667030127407130157111382035819 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 49417518716582620303259732071051824053759018226115819066889382257375730288640 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 74290662539043924602687830823815198916841647350857056271683714907743899524013 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 28508613735938631395461648022612357603901640225450038339404208719445937126538 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 112191886966356173095848917212153702545227279327668775809591040421051908304198 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 26136814037584892206061388057272621522504116989069085375356592870474037106591 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 16898371946694092999963587290693119514853061744947520771685632882437569860924 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 1912824467462457786502515537448286249495208060499493160886606118044094805695 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 5652260984782622804090111443168048729619564521521758083072183175282195186598 80
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 41601114627846286085325628530822920273722000788911259334314644950193906679013 82
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 50640319218920492879695899412781812107061062549276720184146866883585849547238 77
UVM_ERROR @ 209323576 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 209323576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_mem_tl_access_resuming 28688485965187773843302149443127516675566343802391295498339329912635213453432 77
UVM_ERROR @ 60715128 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 60715128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 33324054838440925487103631769921347364177906735222093727148658066299827282496 84
UVM_ERROR @ 6621744810 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6621744810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 10833370485359672140442353171583681252805748411836872774896056233693598000745 78
UVM_ERROR @ 256463194 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 256463194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 71183964276420389253139583899774756119986226374117748557814525053640111638289 79
UVM_ERROR @ 1827407739 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1827407739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 53728480398367001153245786561996743063258659824102449151445503803361160790819 78
UVM_ERROR @ 86303366 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 86303366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 45019827910938890725837885549551699733052251184290405996358755670431042579372 78
UVM_ERROR @ 169924005 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 169924005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 61347937946224600983726785533580564668302418892680573074694194038529882357449 78
UVM_ERROR @ 339177962 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 339177962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 14328193398170464274566277131274864914895736745620993062951218065937042863607 78
UVM_ERROR @ 125332602 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 125332602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 38358195123071707949885063523758785709576235453467446351575767628857732075902 83
UVM_ERROR @ 2213874849 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2213874849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 62917122250018825175563233842292556720987085915393550518611612633364313376430 80
UVM_ERROR @ 863686346 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 863686346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 54011601464575045265588898795413009862154498683470297142598933939407493927236 79
UVM_ERROR @ 1410625175 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1410625175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 108160305570642905717146034741232056280427905368985047135101674162676828721022 79
UVM_ERROR @ 2110303268 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2110303268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 49146087626785704564537689702377924759441079700643122637310526777819624076430 99
UVM_ERROR @ 3697606772 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3697606772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 753104768841024070428942172497859357981848802845942560444945149323405023835 77
UVM_ERROR @ 135997921 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 135997921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 105769150741884722429896026732921711555872824028316906880647321157103503080605 77
UVM_ERROR @ 102254113 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 102254113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 37694878722026005788388990505103984168189479995239680356031351396739065357302 77
UVM_ERROR @ 107289131 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 107289131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 32867395200946090560430157437474548030459417307186925058052287829341571696134 77
UVM_ERROR @ 327587488 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 327587488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 22664322559789291402572068167175414359242689622857022878721688326231466984464 77
UVM_ERROR @ 27871034 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27871034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 87659444861631632403549873407584702039102152705282463773650859313547610074381 107
UVM_ERROR @ 2944972166 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2944972166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 65480636973141871624628445313884241034980852746430717798432493550972027352295 103
UVM_ERROR @ 1309127874 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1309127874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 60830104608878082853027922131820203243307354190247229697389487711697913519489 85
UVM_ERROR @ 7711719686 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7711719686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 31609572025911904203992473892205762372853624330781045981525046153318470564839 79
UVM_ERROR @ 597588693 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 597588693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 40487061504773155948033593311563808257976946897043400469559932578147170005192 84
UVM_ERROR @ 3137150063 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3137150063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 65384254153987134074211425980196305322995405220346279801115898817035486940582 78
UVM_ERROR @ 447766963 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 447766963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 50385912609286907941812530550637346038820716220787425813183842304245790309108 81
UVM_ERROR @ 2385459348 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2385459348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 88272304047826011573007414426364845492360335330813781683170650285000109665053 81
UVM_ERROR @ 1296945203 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1296945203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 24079371367295193511630134248202897088577561183481635289298696414658219088120 78
UVM_ERROR @ 345216080 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 345216080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 2400945732780640550487688849691861000365432948210278064926111731781050369701 78
UVM_ERROR @ 79991350 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 79991350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 94378132412105432784303237725567132692437209416153727015948375646418141425595 78
UVM_ERROR @ 127886605 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 127886605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 110361056915878791909343709620221597249444997027004944923333203515292983235548 78
UVM_ERROR @ 140985153 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 140985153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 20312670027562754729148243365609092295765662655110087248024475191383090338078 80
UVM_ERROR @ 1798410689 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1798410689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 104341024835662393056989427111522462485469979293238636458094101268746315553668 80
UVM_ERROR @ 433301594 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 433301594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 109493574604082266444452198465977198110680029746801077223897108192269834593874 78
UVM_ERROR @ 62751683 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 62751683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 24541970291484338877341544543637047403253358640191796246877931096062951292443 78
UVM_ERROR @ 308508190 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 308508190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 112725254830675543254564870106986216722334376927441875120945266773329145804950 77
UVM_ERROR @ 320064549 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3810271918 [0xe31c22ae] vs 0 [0x0])
UVM_INFO @ 320064549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_jtag_dmi_debug_disabled 113726693133171103506355029609624865988388534786518980299866854510905650317495 77
UVM_ERROR @ 207336614 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4276000887 [0xfede9877] vs 0 [0x0])
UVM_INFO @ 207336614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 61139416037427741043438186437170104683310283335084616991978116394048796769964 80
UVM_ERROR @ 524257044 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3746400696 [0xdf4d89b8] vs 0 [0x0])
UVM_INFO @ 524257044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 96444565002286541543335924999854202652424828673875328466318078075107212215492 83
UVM_ERROR @ 2938259591 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (357346673 [0x154cad71] vs 0 [0x0])
UVM_INFO @ 2938259591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 14529478899798905994455688380970419961530079993266751154394364258189492414369 100
UVM_ERROR @ 1017557791 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (63231642 [0x3c4d69a] vs 0 [0x0])
UVM_INFO @ 1017557791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 17734381949151111263190568414067522016672151209581901613945163699458477478006 81
UVM_ERROR @ 1458485887 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1708071875 [0x65cf1bc3] vs 0 [0x0])
UVM_INFO @ 1458485887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 114684680944570011358188959788139189982194294023313512415484026843225249729249 78
UVM_ERROR @ 154924980 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2581794016 [0x99e30ce0] vs 0 [0x0])
UVM_INFO @ 154924980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 20576937604386989209581562553438783293713224398963224153970865391425876138515 79
UVM_ERROR @ 818031274 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (146127626 [0x8b5bb0a] vs 0 [0x0])
UVM_INFO @ 818031274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 42624701166937967986277898191300462234974984287938888153783096552996576019396 81
UVM_ERROR @ 7592753780 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (9937033 [0x97a089] vs 0 [0x0])
UVM_INFO @ 7592753780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 98986689782070879561422606276876144601162234442215193983433729879352597329123 81
UVM_ERROR @ 2913588843 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1999472358 [0x772d86e6] vs 0 [0x0])
UVM_INFO @ 2913588843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 75258501519895391508258027796832367973682501419469450183083884917450402387458 78
UVM_ERROR @ 275330055 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2459052480 [0x929229c0] vs 0 [0x0])
UVM_INFO @ 275330055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 72223778767847016603741594629916663399528134307898297146380879074415221942359 87
UVM_ERROR @ 9663287063 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (164179245 [0x9c92d2d] vs 0 [0x0])
UVM_INFO @ 9663287063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
rv_dm_stress_all_with_rand_reset 12705176229401446225572204288869937409577560358159712658544789811822672210611 113
UVM_FATAL @ 2509359759 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2509359759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 4863074208421871257133804563834603548679783660248836275385954752134930338641 86
UVM_FATAL @ 4266319157 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 4266319157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 25626740679202954462709247833209805522475681543257139021812772474869631147366 140
UVM_FATAL @ 5922879508 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5922879508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 71575283372035715625584383711934236717669982832170826643927573554185547385189 88
UVM_FATAL @ 3250144641 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3250144641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])
rv_dm_buffered_enable 49232660221511815000299393795582774522109016062125574498603921981193614347275 88
UVM_ERROR @ 267471016 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 267471016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_buffered_enable 39992482162238410188432365287616232762873397141747400803709149220288461042533 84
UVM_ERROR @ 92546899 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 92546899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_buffered_enable 35684400360943272198051429095327042540287784906141694597360773297107166784132 88
UVM_ERROR @ 513322272 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 513322272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
rv_dm_stress_all 26273918238918948220458527759137409626557552974286440386499479946958756020506 None
Job timed out after 180 minutes
rv_dm_stress_all 952168724068387621824258924135723931222104793959567153813831948302420321704 None
Job timed out after 180 minutes
rv_dm_stress_all 34222211311508906070512510197723518639611033327205174544552437622323561433861 None
Job timed out after 180 minutes
rv_dm_stress_all 115300352731610975758176955218499996156261982644892925022462792523967364004959 None
Job timed out after 180 minutes