Simulation Results: dma

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.61 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 80.65 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 33.000s 288.691us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 35.000s 281.283us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 35.000s 1952.987us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 24.015us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 63.049us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 15.000s 2075.149us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 8.000s 615.762us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 45.029us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 63.049us 20 20 100.00
dma_csr_aliasing 8.000s 615.762us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 104.000s 14522.221us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 553.000s 40066.667us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 714.000s 248969.394us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 714.000s 248969.394us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 553.000s 40066.667us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 949.000s 349559.689us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 714.000s 248969.394us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 45.000s 1180.863us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 324.000s 22744.426us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 30.000s 18.632us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 16.606us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 5.000s 2359.417us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 5.000s 2359.417us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 24.015us 5 5 100.00
dma_csr_rw 2.000s 63.049us 20 20 100.00
dma_csr_aliasing 8.000s 615.762us 5 5 100.00
dma_same_csr_outstanding 3.000s 48.034us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 24.015us 5 5 100.00
dma_csr_rw 2.000s 63.049us 20 20 100.00
dma_csr_aliasing 8.000s 615.762us 5 5 100.00
dma_same_csr_outstanding 3.000s 48.034us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 54.000s 4414.808us 5 5 100.00
dma_generic_stress 949.000s 349559.689us 5 5 100.00
dma_handshake_stress 714.000s 248969.394us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 35.000s 1120.490us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 30.000s 108.242us 5 5 100.00
dma_tl_intg_err 4.000s 182.846us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 190.000s 31973.183us 25 25 100.00
dma_longer_transfer 32.000s 148.800us 5 5 100.00
dma_stress_all_with_rand_reset 44.000s 3106.240us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 70281387910738864073674996199146157209754716987790608380038779209410478560462 118
UVM_ERROR @ 3106239801ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3106239801ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---