Simulation Results: keymgr

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 98.48 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.04 %
  • toggle
  • 98.62 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.22%
V2S
98.96%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 15.210s 1376.320us 50 50 100.00
random 50 50 100.00
keymgr_random 46.160s 1864.721us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.720s 23.582us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 25.850s 5112.073us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 11.270s 367.633us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.160s 53.384us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
keymgr_csr_aliasing 11.270s 367.633us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 48 50 96.00
keymgr_cfg_regwen 84.600s 2047.306us 48 50 96.00
sideload 200 200 100.00
keymgr_sideload 28.760s 1590.652us 50 50 100.00
keymgr_sideload_kmac 42.750s 10419.897us 50 50 100.00
keymgr_sideload_aes 31.190s 2284.397us 50 50 100.00
keymgr_sideload_otbn 47.210s 3339.329us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 38.640s 1841.505us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 7.170s 311.636us 49 50 98.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 11.220s 2588.811us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 54.020s 13354.833us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 52.390s 2798.413us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 23.000s 3983.203us 49 50 98.00
stress_all 49 50 98.00
keymgr_stress_all 281.390s 11300.820us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.250s 67.294us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.320s 17.078us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.250s 161.321us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.250s 161.321us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.720s 23.582us 5 5 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
keymgr_csr_aliasing 11.270s 367.633us 5 5 100.00
keymgr_same_csr_outstanding 4.390s 114.611us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.720s 23.582us 5 5 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
keymgr_csr_aliasing 11.270s 367.633us 5 5 100.00
keymgr_same_csr_outstanding 4.390s 114.611us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
keymgr_tl_intg_err 9.970s 283.739us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.090s 729.129us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.090s 729.129us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.090s 729.129us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.090s 729.129us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.720s 3865.702us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.970s 283.739us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.090s 729.129us 20 20 100.00
sec_cm_op_config_regwen 48 50 96.00
keymgr_cfg_regwen 84.600s 2047.306us 48 50 96.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 46.160s 1864.721us 50 50 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 46.160s 1864.721us 50 50 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 46.160s 1864.721us 50 50 100.00
keymgr_csr_rw 1.630s 120.858us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 7.170s 311.636us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 52.390s 2798.413us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 52.390s 2798.413us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 46.160s 1864.721us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 18.540s 832.089us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_ctrl_fsm_consistency 49 50 98.00
keymgr_custom_cm 25.620s 1112.862us 49 50 98.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 7.170s 311.636us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 49 50 98.00
keymgr_custom_cm 25.620s 1112.862us 49 50 98.00
sec_cm_kmac_if_done_ctrl_consistency 49 50 98.00
keymgr_custom_cm 25.620s 1112.862us 49 50 98.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 49 50 98.00
keymgr_custom_cm 25.620s 1112.862us 49 50 98.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 19.400s 692.368us 5 5 100.00
sec_cm_ctrl_key_integrity 49 50 98.00
keymgr_custom_cm 25.620s 1112.862us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
keymgr_stress_all_with_rand_reset 31.090s 8163.261us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 71555009388098441044935706188183849978760327470087128669712298376351115572870 263
UVM_ERROR @ 126095645 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 126095645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64202164907684478009665411886853982494362619465380729309315804324174535398820 550
UVM_ERROR @ 449837937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 449837937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25217910140512772062156708992541457936685071140726032692694324346174224263933 890
UVM_ERROR @ 800570998 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 800570998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 75152575584482470689730121647124330070868031023834243799938920641223327420328 443
UVM_ERROR @ 2364254062 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2364254062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 77686370609318999604732430535319737890545984221239631092280871364250103725970 163
UVM_ERROR @ 106496992 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106496992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 101276936123844284450584235081821323642622531858148654032787201138073246499065 310
UVM_ERROR @ 475788260 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 475788260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17548698151159327143602553326285606459496717342154283581595141249563413499545 527
UVM_ERROR @ 410518774 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 410518774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 76938711782649052248699537557011079329157704355673566635405146531558836317149 1047
UVM_ERROR @ 307769449 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 307769449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26620936421219833056526964948662095514033307249585752334230548164723584804761 305
UVM_ERROR @ 187264339 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 187264339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 59761783113972054110906695151080087995783314653859597568368839596737901225770 536
UVM_ERROR @ 472076515 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 472076515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17354111640524216430443341544785138402391742248249412519429077736154092479890 366
UVM_ERROR @ 211088494 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 211088494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19928268126564571515944060858051220738710346648447278826464921147702447812774 757
UVM_ERROR @ 957313566 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 957313566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28786513863852071491428774340177246299121853388225100298759477353166131162029 172
UVM_ERROR @ 557584777 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 557584777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68757064308552167045966996926488998909285112329806744322417732069525032111342 494
UVM_ERROR @ 267176038 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 267176038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113646096201728543727029167976747674354949456628047629285408576282919318930288 143
UVM_ERROR @ 217520773 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217520773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113498391203557091116166212698029838905436741682646522005273440786781720692833 106
UVM_ERROR @ 468411400 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 468411400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 38957614213909061759242030091375427012687492223794965425820181076932767818601 270
UVM_ERROR @ 619729145 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 619729145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42904952079349009986327059378238864187002556481192178217648766677645220249086 603
UVM_ERROR @ 1245534303 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1245534303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 90151546063433330610134334633627862014089460946469174202835554950820413947730 979
UVM_ERROR @ 926208888 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 926208888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all_with_rand_reset 111575293033593294998913338008513798071999844771452978578618097584562504875653 245
UVM_ERROR @ 119869418 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4
UVM_INFO @ 119869418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_kmac_rsp_err 86564365388620725076177531379798343133279105951705183766449734451612803793739 128
UVM_ERROR @ 4260146 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 4260146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 17566317804196342487158080520500859376953888172067933542706703017417062489496 134
UVM_ERROR @ 10325355 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 10325355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 57888386909455354768597864453145802447642997644503403359053680521134854476231 817
UVM_ERROR @ 291073630 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 291073630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_custom_cm 115043193789478573208601455781571002517241548513393273917049197061957377642225 224
UVM_ERROR @ 55096622 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 55096622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all_with_rand_reset 75814757673626025003331199742632557834446497397949760346807385029908384314456 1113
UVM_ERROR @ 946222371 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
UVM_INFO @ 946222371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start
keymgr_cfg_regwen 97261137699004847902351470558298734773799378976465595900238944450792943660528 86
UVM_ERROR @ 7278207 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 7278207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes
keymgr_lc_disable 93613033750304446838526634744796918457631988602923011910980417232197021967389 443
UVM_ERROR @ 183875921 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5408461793443109681400701245156756893308824820698790680695160414374153904712444635885312178785546360320940517458704303912478978526047908777165957705934455 [0x674402b46a565ae9799d6cc5f590c82309a327d7dc73a35f951ea8134816870dc906a7fd0e68eccc63822f54010fbe3dfb3f446188548456f10dacbe5ca6a677] vs 5408461793443109681400701245156756893308824820698790680695160414374153904712444635885312178785546360320940517458704303912478978526047908777165957705934455 [0x674402b46a565ae9799d6cc5f590c82309a327d7dc73a35f951ea8134816870dc906a7fd0e68eccc63822f54010fbe3dfb3f446188548456f10dacbe5ca6a677]) AES key at state StCreatorRootKey for Attestation Aes
UVM_INFO @ 183875921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*])
keymgr_sync_async_fault_cross 99886050982724050203458121311065289844672377414664200022598560970179275468389 150
UVM_ERROR @ 293087778 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 293087778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---