Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.79 %
  • code
  • 89.01 %
  • assert
  • 96.13 %
  • func
  • 96.22 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.46 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 10.930s 201.695us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.450s 21.282us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.310s 15.145us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.420s 381.454us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.760s 48.290us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.050s 309.404us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.310s 15.145us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 48.290us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.140s 706.681us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.130s 360.685us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.250s 17.760us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.940s 700.546us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 17.870s 4209.937us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_prog_failure 4.940s 700.546us 50 50 100.00
lc_ctrl_errors 17.870s 4209.937us 50 50 100.00
lc_ctrl_security_escalation 11.860s 398.449us 50 50 100.00
lc_ctrl_jtag_state_failure 90.930s 20253.256us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.850s 3262.477us 20 20 100.00
lc_ctrl_jtag_errors 108.630s 20554.048us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 2.840s 252.972us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.290s 583.404us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.280s 4802.496us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.870s 1959.323us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.140s 170.080us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.490s 1851.530us 10 10 100.00
lc_ctrl_jtag_alert_test 1.960s 56.853us 10 10 100.00
lc_ctrl_jtag_smoke 9.660s 431.989us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.750s 2442.110us 20 20 100.00
lc_ctrl_jtag_prog_failure 18.850s 3262.477us 20 20 100.00
lc_ctrl_jtag_errors 108.630s 20554.048us 20 20 100.00
lc_ctrl_jtag_access 22.190s 4243.259us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 31.160s 6139.920us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.810s 17979.524us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.470s 55.872us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 367.970s 44454.816us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.570s 25.528us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.450s 134.500us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.450s 134.500us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.450s 21.282us 5 5 100.00
lc_ctrl_csr_rw 1.310s 15.145us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 48.290us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.210s 94.783us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.450s 21.282us 5 5 100.00
lc_ctrl_csr_rw 1.310s 15.145us 20 20 100.00
lc_ctrl_csr_aliasing 1.760s 48.290us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.210s 94.783us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 2.900s 328.750us 20 20 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 2.900s 328.750us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.130s 360.685us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 15.630s 337.077us 50 50 100.00
lc_ctrl_sec_cm 8.430s 976.297us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.860s 398.449us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.140s 706.681us 50 50 100.00
lc_ctrl_jtag_state_post_trans 26.750s 2442.110us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.090s 845.241us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.090s 845.241us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 22.740s 1102.878us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.470s 1066.434us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.470s 1066.434us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 117.380s 5395.196us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 36514440895695191525223532447809111744417783819973815335111574135185105973340 9592
UVM_ERROR @ 8907805599 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8907805599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10389704439464410524166186630445977563146354781225780858877675352529529635896 194
UVM_ERROR @ 217018923 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217018923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110721483092921683001377908419243608651653927984958992740276069860354048652871 150
UVM_ERROR @ 209991986 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 209991986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12071817212255909388494372342222144466240874940879481443168493183662891796876 1385
UVM_ERROR @ 888865870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 888865870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73816380616678760913051555870966234238920692988789444317625396492605588821145 3445
UVM_ERROR @ 17569361418 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17569361418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106164253375886689359051846339498515332539896437464202790477934810631872678598 468
UVM_ERROR @ 633122830 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 633122830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 380336758290659559258093785955609569605923012153534850852144059323319023119 1594
UVM_ERROR @ 3555976534 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3555976534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85328123367242077829853602396586338070369844665228557151467438693113584540886 5478
UVM_ERROR @ 699359871 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 699359871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99585218476431082904645306619444727598175817998594725645079629538110514141471 6681
UVM_ERROR @ 2201647609 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2201647609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9437809604810369139848259330901225385704281856324473934682862187260411236375 161
UVM_ERROR @ 803417191 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 803417191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106847937495602563319381808761009038451434575214434005895238583421704179850331 3649
UVM_ERROR @ 5085225193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5085225193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96766480174858489287092929836409180108776475344290846250521132311648567055536 152
UVM_ERROR @ 2077055703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2077055703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 111195508289261437239232862070774394247916692909463376566893047615931529448442 8471
UVM_ERROR @ 1690563488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1690563488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35953297005161970933158953132544500565365005731839494480856802518471991062488 2532
UVM_ERROR @ 2648666002 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2648666002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42824592254808489637084550354171281656294430325967212149698887184221263619889 204
UVM_ERROR @ 812411184 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 812411184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86406132854266811750340200022052895074563375517855151369711308945895916573021 151
UVM_ERROR @ 109285347 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 109285347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92797679189387121150979320339903631059270321187400139075209441356762234039060 8628
UVM_ERROR @ 3774752271 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3774752271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102316585779971017143281076212050565571995259627459641990859918053087065088145 1298
UVM_ERROR @ 4813486806 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4813486806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53005663280501279192214082568341277083026495038994061683959342035930114789606 1651
UVM_ERROR @ 2573184253 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2573184253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44351668618819349095567084125355305000944202718395943443180825654067125949971 200
UVM_ERROR @ 228373858 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 228373858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14564448618934300258587272081320668442237235641319497363804931450946929747371 194
UVM_ERROR @ 225290307 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 225290307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108826169888099003186436226557727483897099370652527863929194555853863637643441 197
UVM_ERROR @ 123795792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123795792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104838207805662933583020320504227049175422507347685746498058190827776544855760 3938
UVM_ERROR @ 14003072245 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14003072245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103632784310208996694432107651726947897343516506498362842360488906232781829323 630
UVM_ERROR @ 5798294356 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5798294356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108470692478963880984259900209953008235104103272086731996943252840092612556503 2510
UVM_ERROR @ 18258581416 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18258581416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113260606637313512607088733608729206955193983764599248505287720215234006712616 156
UVM_ERROR @ 1530255071 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1530255071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 62388558129770237381735370100928724251032518460468054233667204801336709501289 16950
UVM_ERROR @ 5395196098 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 5395196098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115335626012459157136474619133500204941165995209304465880861503202568200096756 1062
UVM_ERROR @ 524185767 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 524185767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
lc_ctrl_stress_all_with_rand_reset 78173755800257912928206169794466420290991403747007427641261382451836926292982 None
Job timed out after 180 minutes
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 19666942256561738944391474751213611374974607373148987487746918124579238478501 3903
UVM_ERROR @ 26571775469 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 26571775469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---