Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.85 %
  • code
  • 89.05 %
  • assert
  • 96.28 %
  • func
  • 96.22 %
  • line
  • 97.87 %
  • branch
  • 97.06 %
  • cond
  • 82.59 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
V3
54.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.620s 127.565us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.310s 39.129us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.300s 16.340us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.950s 468.195us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.540s 17.188us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.940s 53.361us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.300s 16.340us 20 20 100.00
lc_ctrl_csr_aliasing 1.540s 17.188us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.470s 196.251us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.180s 698.050us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.350s 13.988us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.130s 360.031us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 15.290s 9634.724us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_prog_failure 5.130s 360.031us 50 50 100.00
lc_ctrl_errors 15.290s 9634.724us 50 50 100.00
lc_ctrl_security_escalation 15.140s 584.674us 50 50 100.00
lc_ctrl_jtag_state_failure 92.380s 17962.152us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.980s 611.609us 20 20 100.00
lc_ctrl_jtag_errors 80.410s 4665.579us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.650s 193.735us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.810s 521.194us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.920s 755.905us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.990s 8700.622us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.930s 53.936us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.220s 361.967us 10 10 100.00
lc_ctrl_jtag_alert_test 1.800s 36.446us 10 10 100.00
lc_ctrl_jtag_smoke 9.860s 5169.874us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.410s 17785.070us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.980s 611.609us 20 20 100.00
lc_ctrl_jtag_errors 80.410s 4665.579us 20 20 100.00
lc_ctrl_jtag_access 26.810s 3093.935us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 24.630s 1157.716us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 16.050s 807.308us 9 10 90.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.430s 38.415us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 428.720s 73191.708us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.570s 50.365us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.390s 443.564us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.390s 443.564us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 39.129us 5 5 100.00
lc_ctrl_csr_rw 1.300s 16.340us 20 20 100.00
lc_ctrl_csr_aliasing 1.540s 17.188us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.030s 220.035us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 39.129us 5 5 100.00
lc_ctrl_csr_rw 1.300s 16.340us 20 20 100.00
lc_ctrl_csr_aliasing 1.540s 17.188us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.030s 220.035us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.300s 127.252us 20 20 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.300s 127.252us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.180s 698.050us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.900s 1797.981us 50 50 100.00
lc_ctrl_sec_cm 10.100s 412.106us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 15.140s 584.674us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.470s 196.251us 50 50 100.00
lc_ctrl_jtag_state_post_trans 22.410s 17785.070us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.990s 1200.334us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.990s 1200.334us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.920s 1770.101us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.270s 563.515us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.270s 563.515us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 50 54.00
lc_ctrl_stress_all_with_rand_reset 123.130s 5132.689us 27 50 54.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 82643803659667508028968957641999296433676667200859289375073308224726827002258 4953
UVM_ERROR @ 2263516424 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2263516424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42236641028043037829815815351746650028250106673146702552152302771977989814958 465
UVM_ERROR @ 1193303796 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1193303796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81697434848862452251323491129848072655753508089857149015579876595791517569694 4173
UVM_ERROR @ 2365437747 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2365437747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28149234759886792667851046677503821654625250355581376840763162296991546135257 2506
UVM_ERROR @ 300146635 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 300146635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38074123983460229638635029226701344250244829689289967529115626467107733410719 2943
UVM_ERROR @ 3679069397 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3679069397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10615442117583774166718535949332284776130980030048253078952520112979896489742 3013
UVM_ERROR @ 2653243123 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2653243123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98857476089776685371218546064673691572073717297455844241934115143633626367577 740
UVM_ERROR @ 6925553073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6925553073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105701870231878899763640235749175410763601921044721555780565425754677217149717 1207
UVM_ERROR @ 1816457241 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1816457241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13796757310165375343156159513930871582885978926008174569338403756596871464391 2585
UVM_ERROR @ 16590619273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16590619273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68406343500197278961759743776543886527879940374961309737938766990628172231341 151
UVM_ERROR @ 207468732 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 207468732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51654584764457901292631731933023750177847826264800637327345156035736168877664 157
UVM_ERROR @ 3740932215 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3740932215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29165935204328564928643870074389090078899056290131236609950026865134934078797 150
UVM_ERROR @ 212469337 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 212469337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84702885225640844729521015207607593827706016069868300343319591564562065594087 3356
UVM_ERROR @ 1628132462 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1628132462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9376054341416329443258611599479915555146850654245505238854142084754693899039 2060
UVM_ERROR @ 5714894975 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5714894975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109725509596196156443745741882733090865998982550507159599875042457546788069655 438
UVM_ERROR @ 1704984958 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1704984958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28704360094914035669255380806509924898037676664909199511713207978595277380209 6437
UVM_ERROR @ 1516930330 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1516930330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26870835318157162611026026707901449646339001963799985417046026048056110408683 1165
UVM_ERROR @ 4460412981 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4460412981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47965738618196400196316745165326671184300574463119067145791342711977947194927 3636
UVM_ERROR @ 5611118941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5611118941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69050718631442032228487301266502832387486093993718207017898852511178421679930 208
UVM_ERROR @ 568796179 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 568796179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6519908823706614997562237714615407920578649357084532174188454273249487633948 1663
UVM_ERROR @ 7760270640 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7760270640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69282471766384429881825417290070335092323394401889392263751730418847064008880 9613
UVM_ERROR @ 10900780426 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10900780426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!
lc_ctrl_jtag_priority 63558543718758047264607681929891797187092567743481304619656008855691959176430 148
UVM_FATAL @ 10010275469 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
UVM_INFO @ 10010275469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 19556757318385749759707296358434183788788745914146034766671347631984672943718 7693
UVM_ERROR @ 2196905019 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2196905019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16531400191852528911774224870875978278093601585852649419156059929394748294855 3754
UVM_ERROR @ 1015125399 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 1015125399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---