Simulation Results: sram_ctrl/main

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 96.96 %
  • assert
  • 96.46 %
  • func
  • 96.60 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 9.000s 1445.838us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 14.450us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 84.056us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.000s 54.808us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 80.221us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 353.538us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 84.056us 20 20 100.00
sram_ctrl_csr_aliasing 1.000s 80.221us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 292.000s 21104.567us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 118.000s 4379.598us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 48.000s 7721.257us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 330.000s 51569.036us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 178.000s 17977.493us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 82.000s 69398.648us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 71.000s 28189.683us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 45.000s 75578.339us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 7.000s 2792.061us 5 5 100.00
sram_ctrl_partial_access_b2b 419.000s 24354.450us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 8.000s 4103.884us 0 5 0.00
sram_ctrl_throughput_w_partial_write 7.000s 706.584us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 2739.415us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 19.000s 11955.145us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 993.876us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 772.000s 1420492.555us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 24.949us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 1565.205us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 1565.205us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.450us 5 5 100.00
sram_ctrl_csr_rw 2.000s 84.056us 20 20 100.00
sram_ctrl_csr_aliasing 1.000s 80.221us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 12.859us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.450us 5 5 100.00
sram_ctrl_csr_rw 2.000s 84.056us 20 20 100.00
sram_ctrl_csr_aliasing 1.000s 80.221us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 12.859us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 40.000s 7083.855us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 285.479us 20 20 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.000s 285.479us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 19.000s 11955.145us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 19.000s 11955.145us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 84.056us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 45.000s 75578.339us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 45.000s 75578.339us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 45.000s 75578.339us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 71.000s 28189.683us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 6.000s 4146.154us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 40.000s 7083.855us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 7.000s 2895.905us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 1445.838us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 1445.838us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 45.000s 75578.339us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 71.000s 28189.683us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 9.000s 1445.838us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 3441.633us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 38.000s 6801.242us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 68696206746037333552235636427782865837207682467628898499322153427761100992557 102
UVM_FATAL @ 1369273442 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1369273442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 111317058899185940837463097816145041347180416012759260224361072772855305252374 102
UVM_FATAL @ 3886343922 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 3886343922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 32146395185037174974999658602264770343394750623162272493063872316601371127509 102
UVM_FATAL @ 1340591347 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1340591347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 31305682703482349512768294129300123264096649076858756817503544957163975260289 102
UVM_FATAL @ 2739415218 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2739415218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 91126330623625549167117158551795103161360891936955803205939341611052084013049 102
UVM_FATAL @ 666462141 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 666462141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 39435353262625792835129411224653547861584895827626829542854101015522419108396 102
UVM_FATAL @ 691230649 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 691230649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 13555968893095654353227868329831578158288335611180988645562736956029306264538 102
UVM_FATAL @ 4103884217 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 4103884217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 22807898178077311874336869280982688939957663818531106812821933141049306368181 102
UVM_FATAL @ 670398863 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 670398863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 4129916231614638388679743369285232454121322037174740211217183959443108207590 102
UVM_FATAL @ 691712006 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 691712006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46909314072438252679967591884223606215135730735897976303113995989801016465386 102
UVM_FATAL @ 925507466 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 925507466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---