Simulation Results: dma

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 78.69 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
93.55%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 378.462us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 10.000s 832.293us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 390.997us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 54.218us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 32.070us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 14.000s 7439.717us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 9.000s 1106.434us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 25.562us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 32.070us 20 20 100.00
dma_csr_aliasing 9.000s 1106.434us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 156.000s 13392.142us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1093.000s 305959.419us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 952.000s 75663.918us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 952.000s 75663.918us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1093.000s 305959.419us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 975.000s 86268.342us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 952.000s 75663.918us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 13.000s 710.984us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 360.000s 24230.363us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 14.709us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 17.655us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 55.061us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 55.061us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 54.218us 5 5 100.00
dma_csr_rw 2.000s 32.070us 20 20 100.00
dma_csr_aliasing 9.000s 1106.434us 5 5 100.00
dma_same_csr_outstanding 3.000s 374.150us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 54.218us 5 5 100.00
dma_csr_rw 2.000s 32.070us 20 20 100.00
dma_csr_aliasing 9.000s 1106.434us 5 5 100.00
dma_same_csr_outstanding 3.000s 374.150us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 26.000s 1848.037us 5 5 100.00
dma_generic_stress 975.000s 86268.342us 5 5 100.00
dma_handshake_stress 952.000s 75663.918us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 290.726us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 4.000s 362.729us 20 20 100.00
dma_sec_cm 2.000s 23.281us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 29 31 93.55
dma_short_transfer 157.000s 12511.613us 24 25 96.00
dma_longer_transfer 56.000s 2411.315us 5 5 100.00
dma_stress_all_with_rand_reset 3.000s 432.307us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 47481459419128746730846140344052421580289423809561437077752133088430399293344 92
UVM_ERROR @ 432307219ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 432307219ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue
dma_short_transfer 8974271540853611619243082407629849895556152285323348805612049624918141946328 2183
UVM_FATAL @ 200000000000ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---