Simulation Results: edn/edn0

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.71 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.08 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
98.97%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.390s 29.575us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.200s 27.687us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.240s 13.121us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 6.370s 1043.716us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.890s 38.057us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.030s 111.388us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.240s 13.121us 20 20 100.00
edn_csr_aliasing 1.890s 38.057us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.420s 881.467us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.420s 881.467us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.420s 881.467us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.610s 20.764us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.770s 58.458us 200 200 100.00
errs 100 100 100.00
edn_err 1.570s 21.847us 100 100 100.00
disable 90 100 90.00
edn_disable 1.340s 15.404us 50 50 100.00
edn_disable_auto_req_mode 8.720s 500.000us 40 50 80.00
stress_all 50 50 100.00
edn_stress_all 5.770s 308.928us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.250s 12.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.400s 71.309us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.010s 165.980us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.010s 165.980us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.200s 27.687us 5 5 100.00
edn_csr_rw 1.240s 13.121us 20 20 100.00
edn_csr_aliasing 1.890s 38.057us 5 5 100.00
edn_same_csr_outstanding 1.790s 31.515us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.200s 27.687us 5 5 100.00
edn_csr_rw 1.240s 13.121us 20 20 100.00
edn_csr_aliasing 1.890s 38.057us 5 5 100.00
edn_same_csr_outstanding 1.790s 31.515us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.750s 430.399us 20 20 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.070s 16.084us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.770s 58.458us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.770s 58.458us 200 200 100.00
edn_sec_cm 8.450s 741.152us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.770s 58.458us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.750s 430.399us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 109.360s 10175.952us 44 50 88.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 30087658006659625948243067963260123888902666699267363361309687687329482919529 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 50044308550790896346593206957884839803948734957098285223623318561744942964581 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31108439995625838217237171507501531054662243182297230600832709620903092355094 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 41316267921579777814197161659013678783479982016687234175332467898888229115224 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 70429737055900596047683251075445131192383350850286557814269510078455493212539 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 75283345910979505767444769830779721390269925922200978306744333820367700339777 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 47510603427245436813421754030764456603191834851420339589529076546418602159365 88
UVM_FATAL @ 11360265 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00fca9b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 11360265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 39486483220907615042969392222785395614031723682950357366662733668129443314196 88
UVM_FATAL @ 18302262 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001603 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 18302262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66550178683500023251868399212509578305958629399511933143645545213813992306220 88
UVM_FATAL @ 41055900 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x004fa902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 41055900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98709710505614344207915967700475626000576170889294334073350534866757588155517 88
UVM_FATAL @ 55623350 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00e7c6b2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 55623350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 79624087709338105281709221958722427578193103044207820191673577535139920285914 334
UVM_ERROR @ 4171922795 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4171922795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72358285214559788677354336974298001338356758493250769689030154231340273562739 258
UVM_ERROR @ 1780107488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1780107488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 104382023416398181208387207362369575288032430419058571051418486784896962393759 161
UVM_ERROR @ 993005307 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 993005307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 20827910404232850360253752655217346183976871137656757015001574929793749358178 160
UVM_ERROR @ 1293338933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1293338933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91495973587837647774658998764075123093762076408685172356880860542323957948496 342
UVM_ERROR @ 4001988776 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4001988776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 75722217429245453772660760521827283882120209786589688804250433708063103769652 174
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 195959251 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup