Simulation Results: edn/edn1

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.11 %
  • code
  • 95.95 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.280s 17.705us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.050s 62.713us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.940s 32.117us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.400s 694.028us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.480s 45.456us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.710s 36.443us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.940s 32.117us 20 20 100.00
edn_csr_aliasing 1.480s 45.456us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.560s 283.903us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.560s 283.903us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.560s 283.903us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.410s 26.723us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.600s 105.113us 200 200 100.00
errs 100 100 100.00
edn_err 1.630s 39.842us 100 100 100.00
disable 92 100 92.00
edn_disable 1.250s 21.966us 50 50 100.00
edn_disable_auto_req_mode 7.350s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 4.800s 493.887us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.980s 15.139us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.310s 40.818us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.440s 163.456us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.440s 163.456us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.050s 62.713us 5 5 100.00
edn_csr_rw 0.940s 32.117us 20 20 100.00
edn_csr_aliasing 1.480s 45.456us 5 5 100.00
edn_same_csr_outstanding 1.280s 127.088us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.050s 62.713us 5 5 100.00
edn_csr_rw 0.940s 32.117us 20 20 100.00
edn_csr_aliasing 1.480s 45.456us 5 5 100.00
edn_same_csr_outstanding 1.280s 127.088us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 1.920s 417.238us 20 20 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.290s 19.389us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.600s 105.113us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.600s 105.113us 200 200 100.00
edn_sec_cm 4.890s 1223.896us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.600s 105.113us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 1.920s 417.238us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 40 50 80.00
edn_stress_all_with_rand_reset 111.400s 59804.680us 40 50 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 108520504742415988801538636411058194216629730683038348921558585691587026707468 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49053862065891549027325336002064248422505893970938710233302992293941842644773 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 51242792611634827634250661090291732798149982461411344002041703236661480320619 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109311599236220880592476580859962700875754024865295856331568788394393478858842 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66412567637021511354734252756402479065102110008641667717210439598912040112755 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 37046372238062792026549862563128393609772152633897135095569312196456097005747 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 72793628020778766350098371191689019778547915569285351841835488611806452754667 207
UVM_ERROR @ 755705069 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 755705069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 52361461457218735332650920586207567761880932265754175344039690870861089007850 153
UVM_ERROR @ 1180018521 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1180018521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16247388619242804711157631602626205785895946764049283754355341247516653721688 185
UVM_ERROR @ 603316850 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 603316850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 43272511179204497166117069097242257622892155139093265366289686911916353372721 318
UVM_ERROR @ 4556544593 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4556544593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 67202800655627745858735831502022698187850910842664168975323950307850060722245 186
UVM_ERROR @ 1800507580 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1800507580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35252659188833789913737981749485860044416478474653213839369146187525018736846 185
UVM_ERROR @ 1613484224 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1613484224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 88494956302285529343405585539426666535628071818467169412790183362358559065315 142
UVM_ERROR @ 848600942 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 848600942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 53280762860196266380883355860507884685430675029205424267200596668844128875769 140
UVM_ERROR @ 924142125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 924142125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 76136993405369430129619476779928460965493167189990928628337491875560159716585 132
UVM_ERROR @ 163296589 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 163296589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 49047699248775336028345852582661635741679251108202489648743001179924448720769 117
UVM_ERROR @ 781740541 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 781740541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_disable_auto_req_mode 40292285900808585753976157867169035567755912656624255463031611453342377523385 89
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 62140242 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 1854519597792442219843054952115963359418395742080904692912682884467905817134 88
UVM_FATAL @ 28697445 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001fd962 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 28697445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---