Simulation Results: keymgr

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 98.97 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.16 %
  • toggle
  • 98.51 %
  • FSM
  • 100.00 %
Validation stages
V1
99.35%
V2
99.61%
V2S
99.22%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 23.750s 7462.241us 50 50 100.00
random 49 50 98.00
keymgr_random 52.730s 17812.892us 49 50 98.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.740s 25.150us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 13.020s 2076.507us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 7.620s 383.257us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.480s 48.049us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
keymgr_csr_aliasing 7.620s 383.257us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 72.660s 1796.835us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 32.360s 26998.555us 50 50 100.00
keymgr_sideload_kmac 51.360s 6118.823us 50 50 100.00
keymgr_sideload_aes 33.100s 4243.948us 50 50 100.00
keymgr_sideload_otbn 61.760s 8840.926us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 20.590s 2176.142us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 6.060s 270.213us 48 50 96.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 6.390s 175.786us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 41.100s 21507.044us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 53.010s 5707.757us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 25.440s 9186.107us 50 50 100.00
stress_all 49 50 98.00
keymgr_stress_all 467.140s 24454.474us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.210s 65.164us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.510s 48.357us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.980s 158.339us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.980s 158.339us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.740s 25.150us 5 5 100.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
keymgr_csr_aliasing 7.620s 383.257us 5 5 100.00
keymgr_same_csr_outstanding 3.120s 87.177us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.740s 25.150us 5 5 100.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
keymgr_csr_aliasing 7.620s 383.257us 5 5 100.00
keymgr_same_csr_outstanding 3.120s 87.177us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
keymgr_tl_intg_err 8.560s 211.595us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.110s 661.385us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.110s 661.385us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.110s 661.385us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.110s 661.385us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.090s 891.812us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.560s 211.595us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.110s 661.385us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 72.660s 1796.835us 50 50 100.00
sec_cm_reseed_config_regwen 69 70 98.57
keymgr_random 52.730s 17812.892us 49 50 98.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
sec_cm_sw_binding_config_regwen 69 70 98.57
keymgr_random 52.730s 17812.892us 49 50 98.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
sec_cm_max_key_ver_config_regwen 69 70 98.57
keymgr_random 52.730s 17812.892us 49 50 98.00
keymgr_csr_rw 1.700s 119.542us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 6.060s 270.213us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 53.010s 5707.757us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 53.010s 5707.757us 50 50 100.00
sec_cm_hw_key_sw_noaccess 49 50 98.00
keymgr_random 52.730s 17812.892us 49 50 98.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 23.070s 3655.479us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 9.530s 1853.361us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 6.060s 270.213us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 9.530s 1853.361us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 9.530s 1853.361us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 9.530s 1853.361us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.640s 561.917us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 9.530s 1853.361us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
keymgr_stress_all_with_rand_reset 25.230s 6441.541us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 43391524038137936136506732555569616583035616639180434471453456176100317822925 225
UVM_ERROR @ 119899550 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119899550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48093764557945918034164910966263069007588119614285953406593486570078546235683 1058
UVM_ERROR @ 364400782 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 364400782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 35041346413108650165274595075778341624972952674102147588389834552168374005760 1366
UVM_ERROR @ 710472154 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 710472154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 6132064917835027025029353775584038357988866247435889947348286546227230210221 245
UVM_ERROR @ 141676004 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 141676004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50411406769356526660183343568958439169527910647915283261012343780484210123232 800
UVM_ERROR @ 1287977917 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1287977917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 29240874712399484827973692469390301330203104172963273158295401246523417969283 283
UVM_ERROR @ 302852951 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 302852951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 3424297541245159800754323919272361099446737718574372776218457439393424476565 655
UVM_ERROR @ 1197177017 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1197177017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95466156837251764667061377434597834340254457816723771903225518642122646727108 158
UVM_ERROR @ 461344841 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 461344841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107572318855155546532179290912372071769331143731801163918929362554623779879558 488
UVM_ERROR @ 644711933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 644711933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78204541257346463752103158687656668432974292201469487419958075437662304814669 878
UVM_ERROR @ 545371341 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 545371341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12547220424076732027466024448397297338422782842588270936531029098620266010599 286
UVM_ERROR @ 534349614 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 534349614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 34797269620154668611197170460142280589820053018197102008845417310358858784530 872
UVM_ERROR @ 3741766409 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3741766409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17463861705160417290812329694222074068955035686817985376749714659561654685302 1283
UVM_ERROR @ 1422403168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1422403168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108016220793239604975567026042627037083463072785830805869648200831315433943732 365
UVM_ERROR @ 165925377 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 165925377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 93853657190879384170277774606821000246038479643160172294558132031806023928622 633
UVM_ERROR @ 246770417 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 246770417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43835325072204432914146461162512044457894840989880949031979975526314049947299 233
UVM_ERROR @ 586849076 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 586849076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50333136150802417673416202978172326057844838992864187788502522238817612225192 1044
UVM_ERROR @ 324155125 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 324155125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108428805752387413888606635651721625577478191511339572374250583480750652795870 102
UVM_ERROR @ 106081665 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106081665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac
keymgr_lc_disable 97270094756461345802624241015377521223638608220632636467354555802661083855810 249
UVM_ERROR @ 26849983 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9941408910649659374519188707195760638686311306577988539176511476502911168277025875211151363036104301896015918801587641340336534573453775027782140359676404 [0xbdd0983391feb4957ea9199ff7e9a7d88e71ee5f005a5bce88e1352527f6a1a1a53c499036ff98d141332494f438cd5107a4e3e9bc04508fd54f6af19d1911f4] vs 9941408910649659374519188707195760638686311306577988539176511476502911168277025875211151363036104301896015918801587641340336534573453775027782140359676404 [0xbdd0983391feb4957ea9199ff7e9a7d88e71ee5f005a5bce88e1352527f6a1a1a53c499036ff98d141332494f438cd5107a4e3e9bc04508fd54f6af19d1911f4]) KMAC key at state StCreatorRootKey for Attestation Kmac
UVM_INFO @ 26849983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_random 85470761628644527538563442497292444280294243022314083383253454146971287526551 94
UVM_ERROR @ 6555904 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6555904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 35720925341562475735191352861638194991717117324702236626737879790886831251387 101
UVM_ERROR @ 12273415 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 12273415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_lc_disable 14711504100106706756963071650319306834755157149756740107952767403994258944604 178
UVM_ERROR @ 23635562 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
UVM_INFO @ 23635562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 100071643685870409328577153297430239662689135837693211979425252878358388455141 2139
UVM_ERROR @ 1473819960 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
UVM_INFO @ 1473819960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all_with_rand_reset 79630419330010778782825665067110148924183167571270598939647107027702820054766 1106
UVM_ERROR @ 3692962123 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3983337306 [0xed6ce75a] vs 3983337306 [0xed6ce75a]) reg name: keymgr_reg_block.sw_share0_output_1
UVM_INFO @ 3692962123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 87016636318153018410006362499073952351504820771607982339206615550703265376449 275
UVM_ERROR @ 308534225 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 308534225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---