Simulation Results

Simulation Results: otbn

19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
95.58 %

code
96.10 %

assert
90.65 %

func
100.00 %

block
99.50 %

line
99.66 %

branch
93.64 %

toggle
93.67 %

FSM
97.44 %

Validation stages

V1		100.00%
V2		98.91%
V2S		98.53%
V3		20.00%
unmapped		100.00%

166/166 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	10.000s	129.291us	1	1	100.00
single_binary				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
csr_hw_reset				5	5	100.00
	otbn_csr_hw_reset	10.000s	54.701us	5	5	100.00
csr_rw				20	20	100.00
	otbn_csr_rw	9.000s	48.852us	20	20	100.00
csr_bit_bash				5	5	100.00
	otbn_csr_bit_bash	12.000s	36.452us	5	5	100.00
csr_aliasing				5	5	100.00
	otbn_csr_aliasing	10.000s	19.332us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	otbn_csr_mem_rw_with_rand_reset	12.000s	26.203us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	otbn_csr_rw	9.000s	48.852us	20	20	100.00
	otbn_csr_aliasing	10.000s	19.332us	5	5	100.00
mem_walk				5	5	100.00
	otbn_mem_walk	121.000s	12304.553us	5	5	100.00
mem_partial_access				5	5	100.00
	otbn_mem_partial_access	57.000s	5556.707us	5	5	100.00

273/276 passed

98.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	48.000s	739.990us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	59.000s	145.998us	1	1	100.00
back_to_back				10	10	100.00
	otbn_multi	228.000s	1630.188us	10	10	100.00
stress_all				10	10	100.00
	otbn_stress_all	867.000s	2851.944us	10	10	100.00
lc_escalation				58	60	96.67
	otbn_escalate	23.000s	61.468us	58	60	96.67
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	7.000s	48.676us	5	5	100.00
sw_errs_fatal_chk				9	10	90.00
	otbn_sw_errs_fatal_chk	21.000s	96.761us	9	10	90.00
alert_test				50	50	100.00
	otbn_alert_test	8.000s	32.312us	50	50	100.00
intr_test				50	50	100.00
	otbn_intr_test	14.000s	33.404us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	otbn_tl_errors	11.000s	196.851us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	otbn_tl_errors	11.000s	196.851us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	otbn_csr_hw_reset	10.000s	54.701us	5	5	100.00
	otbn_csr_rw	9.000s	48.852us	20	20	100.00
	otbn_csr_aliasing	10.000s	19.332us	5	5	100.00
	otbn_same_csr_outstanding	13.000s	43.902us	20	20	100.00
tl_d_partial_access				50	50	100.00
	otbn_csr_hw_reset	10.000s	54.701us	5	5	100.00
	otbn_csr_rw	9.000s	48.852us	20	20	100.00
	otbn_csr_aliasing	10.000s	19.332us	5	5	100.00
	otbn_same_csr_outstanding	13.000s	43.902us	20	20	100.00

V2S

334/339 passed

98.53 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	13.000s	104.367us	10	10	100.00
	otbn_dmem_err	17.000s	115.480us	15	15	100.00
internal_integrity				17	17	100.00
	otbn_alu_bignum_mod_err	19.000s	47.623us	5	5	100.00
	otbn_controller_ispr_rdata_err	10.000s	56.287us	5	5	100.00
	otbn_mac_bignum_acc_err	11.000s	93.315us	5	5	100.00
	otbn_urnd_err	6.000s	41.749us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	12.000s	55.945us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	7.000s	21.827us	2	2	100.00
otbn_non_sec_partial_wipe				10	10	100.00
	otbn_partial_wipe	8.000s	37.627us	10	10	100.00
tl_intg_err				25	25	100.00
	otbn_tl_intg_err	34.000s	178.796us	20	20	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
passthru_mem_tl_intg_err				17	20	85.00
	otbn_passthru_mem_tl_intg_err	58.000s	211.385us	17	20	85.00
prim_fsm_check				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
prim_count_check				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	10.000s	129.291us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	17.000s	115.480us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	13.000s	104.367us	10	10	100.00
sec_cm_bus_integrity				20	20	100.00
	otbn_tl_intg_err	34.000s	178.796us	20	20	100.00
sec_cm_controller_fsm_global_esc				58	60	96.67
	otbn_escalate	23.000s	61.468us	58	60	96.67
sec_cm_controller_fsm_local_esc				40	40	100.00
	otbn_imem_err	13.000s	104.367us	10	10	100.00
	otbn_dmem_err	17.000s	115.480us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	48.676us	5	5	100.00
	otbn_illegal_mem_acc	12.000s	55.945us	5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_controller_fsm_sparse				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_scramble_key_sideload				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_scramble_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	13.000s	104.367us	10	10	100.00
	otbn_dmem_err	17.000s	115.480us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	48.676us	5	5	100.00
	otbn_illegal_mem_acc	12.000s	55.945us	5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_scramble_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_global_esc				58	60	96.67
	otbn_escalate	23.000s	61.468us	58	60	96.67
sec_cm_start_stop_ctrl_fsm_local_esc				40	40	100.00
	otbn_imem_err	13.000s	104.367us	10	10	100.00
	otbn_dmem_err	17.000s	115.480us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	48.676us	5	5	100.00
	otbn_illegal_mem_acc	12.000s	55.945us	5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_start_stop_ctrl_fsm_sparse				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_data_reg_sw_sca				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	8.000s	23.030us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	15.000s	65.528us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	79.000s	833.724us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	79.000s	833.724us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	11.000s	77.435us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_stack_wr_ptr_ctr_redun				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_rf_bignum_data_reg_sw_integrity				10	10	100.00
	otbn_rf_bignum_intg_err	13.000s	227.946us	10	10	100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_loop_stack_ctr_redun				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	11.000s	36.339us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	11.000s	36.339us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	12.000s	38.479us	7	7	100.00
sec_cm_data_mem_sec_wipe				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_instruction_mem_sec_wipe				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_data_reg_sw_sec_wipe				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	228.000s	1630.188us	10	10	100.00
sec_cm_ctrl_flow_count				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_ctrl_flow_sca				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	24.000s	63.033us	5	5	100.00
sec_cm_key_sideload				100	100	100.00
	otbn_single	58.000s	230.485us	100	100	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	otbn_sec_cm	223.000s	4274.691us	5	5	100.00

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	otbn_stress_all_with_rand_reset	556.000s	8671.664us	2	10	20.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	8.000s	64.342us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
	otbn_passthru_mem_tl_intg_err	79098505902509480743336376001092540443327798849951660334922435230381076437464	96	UVM_FATAL @ 83688581 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived. UVM_INFO @ 83688581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	25837301002083781016061519455384188515994603467504448349616302091472594764619	86	UVM_FATAL @ 1913979 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived. UVM_INFO @ 1913979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
	otbn_passthru_mem_tl_intg_err	85526398374104691298610410426816738995403870760651378740991790640469945336050	86	UVM_FATAL @ 4415266 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived. UVM_INFO @ 4415266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	otbn_stress_all_with_rand_reset	73060554968069319318338194303126504554204173392315433270744496686863223183189	356	UVM_ERROR @ 1686648338 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1686648338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	58206152948413441800026706349352096489864155949548981494859422688287950563294	398	UVM_ERROR @ 4004542622 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 4004542622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	44780281614615063280616367511143718097745852399443982472770825817236267326911	281	UVM_ERROR @ 455890627 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 455890627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	97984865735874847218739968200223419668555878093808488316846613991711846063757	164	UVM_ERROR @ 717158612 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 717158612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job returned non-zero exit code
	otbn_sw_errs_fatal_chk	4220940986446577081827245109920981361357223973562404250139000953688409817756	None	[make]: pre_run mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 4220940986446577081827245109920981361357223973562404250139000953688409817756 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries /nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest 2026/04/19 13:58:41 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64... Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
	otbn_stress_all_with_rand_reset	62622592952514027082387971940991532532364253936025051147068566389547091845227	894	UVM_FATAL @ 8671664421 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 8671664421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire
	otbn_stress_all_with_rand_reset	73548209776015893063628546973513220274924020730201723658982897375097632206453	169	UVM_ERROR @ 52135137 ps: (cip_base_vseq.sv:1028) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] expect alert:fatal to fire UVM_INFO @ 52135137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
	otbn_stress_all_with_rand_reset	21544130245621215365338023670973061040978966097968123766726202991226534183773	177	UVM_FATAL @ 3851257285 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 3851257285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	7625962217196446006646229373325097219246024112526943968661742715295178255132	163	UVM_FATAL @ 1219668515 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset) UVM_INFO @ 1219668515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status
	otbn_escalate	78921339787447574080640325052158217805367186298516741064122145647321536580306	105	UVM_ERROR @ 2944717 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status UVM_INFO @ 2944717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_escalate	75604027674361260633212540012185961165595383492974066758274467692872874796067	105	UVM_ERROR @ 12872276 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status UVM_INFO @ 12872276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---